Date: Mon, 3 Feb 1997 12:19:16 +0200 (EET) From: Narvi <narvi@haldjas.folklore.ee> To: Terry Lambert <terry@lambert.org> Cc: gurney_j@resnet.uoregon.edu, hackers@freefall.freebsd.org Subject: Re: performance puzzler Message-ID: <Pine.BSF.3.95.970203111947.16664A-100000@haldjas.folklore.ee> In-Reply-To: <199702021951.MAA08288@phaeton.artisoft.com>
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On Sun, 2 Feb 1997, Terry Lambert wrote: > > > The PCI and EISA standards specify 33MHz as their top end. > > > > Where did I read about 66Mhz revision/mode for PCI? Was it in a dream or > > just a "not supported by anybody yet" possibility as is the 64bit card > > width. Or was it all just a dream or erroneus news article? > > The PCI SIG has been discussing this. Obviously, the 64bit version > can't use the same edge connector because there aren't 32 free lines; > all this "64bit PCI card" hype claimed by video vendors is on-card > data path, not bus data path. I know. The graphics chip (and it's data path) can be of arbitary width. There are at least also 128 bit ones. This is at least one thing I am never confusing :-) Well, at the time (or about the time) PCI came out, there definately was talk about 64 bit PCI slots. > > The 66MHz has also been discussed, but requires a way to key the bus > as to which type of card is present so it can introduce a wait state > per cycle for older cards. Well - the "obvious way" would be making different color connectors and saying - You wanted it you got it. No slower than 66Mhz cards in the <insert a colour here> slots. But it seems that (fortunately) PCI is no longer a PC thing. > > One problem with the design is that the bus chaining used in current > Intel chip designs won't work: you can't send 66MHz signals down a bus > if you have 33MHz cards potentially listening or attempting to master > the bus. This basically means that the Intel PCI bus chips can't > tie all the slots to the same chip lines, if you are going to try > to use the same card connector. This is a win, in that it means that > we will finally get over the 4 slot limit imposed by the line drivers > (which doesn't exist in the Motorola and Apple PCI chipsets because > they were not lazy in their design). It's bad, because it means > new motherboard designs, and PCI has just settled down from the last > minor revision to the spec.. 8-(. Well, the obvious way of doing things would have the main CPU to PCI controller (provided we are going to have such a beast instead of say two independent ones on the motherboard) to be 66Mhz/64 bit one wich would: a) export some (if any) 64 bit/66Mhz PCI slots b) act as a backbone for PCI bridges being 64 bit/66Mhz on one side and having some number of "odinary" slots on the other. b) is of help in the cases of any kind of concurent activity on the PCI bus - both high speed/bandwidth cards and cards making large transfers to each other over the PCI bus. Say I wanted to have in my computer a PCI frame grabber, a PCI graphics board, PCI fast etrhernet adapter, a DSP board, an Adaptec 3940 (well, this is already 5 cards on one PCI bus). It may most efficent if the frame grabber sent its data directlt to the DSP board or the graphics borad (making there be a constant flow of ~27 MB/sec in the case of 640x480x30fps@24bits). Yes, it all is "high end" stuff. But I don't want to get stuck in the next ISA bus witch will just become obsolete and remain still in use for long time. Sander > > > Terry Lambert > terry@lambert.org > --- > Any opinions in this posting are my own and not those of my present > or previous employers. >
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