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Date:      Sun, 24 May 2015 12:20:12 +0000 (UTC)
From:      Andrew Turner <andrew@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r283366 - head/sys/arm/arm
Message-ID:  <201505241220.t4OCKCCp058111@svn.freebsd.org>

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Author: andrew
Date: Sun May 24 12:20:11 2015
New Revision: 283366
URL: https://svnweb.freebsd.org/changeset/base/283366

Log:
  Remove trailing whitespace from sys/arm/arm

Modified:
  head/sys/arm/arm/bcopyinout.S
  head/sys/arm/arm/bcopyinout_xscale.S
  head/sys/arm/arm/blockio.S
  head/sys/arm/arm/bus_space_base.c
  head/sys/arm/arm/busdma_machdep-v6.c
  head/sys/arm/arm/busdma_machdep.c
  head/sys/arm/arm/copystr.S
  head/sys/arm/arm/cpu_asm-v6.S
  head/sys/arm/arm/cpufunc.c
  head/sys/arm/arm/cpufunc_asm_arm11x6.S
  head/sys/arm/arm/cpufunc_asm_arm9.S
  head/sys/arm/arm/cpufunc_asm_armv6.S
  head/sys/arm/arm/cpufunc_asm_armv7.S
  head/sys/arm/arm/cpufunc_asm_xscale_c3.S
  head/sys/arm/arm/cpuinfo.c
  head/sys/arm/arm/db_interface.c
  head/sys/arm/arm/elf_trampoline.c
  head/sys/arm/arm/exception.S
  head/sys/arm/arm/fiq.c
  head/sys/arm/arm/fusu.S
  head/sys/arm/arm/gic.c
  head/sys/arm/arm/intr.c
  head/sys/arm/arm/machdep.c
  head/sys/arm/arm/mp_machdep.c
  head/sys/arm/arm/mpcore_timer.c
  head/sys/arm/arm/nexus.c
  head/sys/arm/arm/physmem.c
  head/sys/arm/arm/pl190.c
  head/sys/arm/arm/pl310.c
  head/sys/arm/arm/pmap-v6-new.c
  head/sys/arm/arm/pmap-v6.c
  head/sys/arm/arm/pmap.c
  head/sys/arm/arm/support.S
  head/sys/arm/arm/swtch.S
  head/sys/arm/arm/trap.c
  head/sys/arm/arm/vfp.c
  head/sys/arm/arm/vm_machdep.c

Modified: head/sys/arm/arm/bcopyinout.S
==============================================================================
--- head/sys/arm/arm/bcopyinout.S	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/bcopyinout.S	Sun May 24 12:20:11 2015	(r283366)
@@ -69,7 +69,7 @@ __FBSDID("$FreeBSD$");
 
 #define SAVE_REGS	stmfd	sp!, {r4-r11}
 #define RESTORE_REGS	ldmfd	sp!, {r4-r11}
-		
+
 #if defined(_ARM_ARCH_5E)
 #define HELLOCPP #
 #define PREFETCH(rx,o)	pld	[ rx , HELLOCPP (o) ]
@@ -88,7 +88,7 @@ __FBSDID("$FreeBSD$");
  * r4-r11 are scratch
  */
 ENTRY(copyin)
-	/* Quick exit if length is zero */	
+	/* Quick exit if length is zero */
 	teq	r2, #0
 	moveq	r0, #0
 	RETeq
@@ -326,7 +326,7 @@ END(copyin)
  */
 
 ENTRY(copyout)
-	/* Quick exit if length is zero */	
+	/* Quick exit if length is zero */
 	teq	r2, #0
 	moveq	r0, #0
 	RETeq

Modified: head/sys/arm/arm/bcopyinout_xscale.S
==============================================================================
--- head/sys/arm/arm/bcopyinout_xscale.S	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/bcopyinout_xscale.S	Sun May 24 12:20:11 2015	(r283366)
@@ -85,7 +85,7 @@ ENTRY(copyin)
 	ldmfd   sp!, {r0-r2, r4, lr}
 	moveq	r0, #0
 	RETeq
-					
+
 .Lnormal:
 	stmfd	sp!, {r10-r11, lr}
 
@@ -527,8 +527,8 @@ ENTRY(copyout)
 	ldmfd   sp!, {r0-r2, r4, lr}
 	moveq	r0, #0
 	RETeq
-	
-.Lnormale:									
+
+.Lnormale:
 	stmfd	sp!, {r10-r11, lr}
 
 	GET_PCB(r10)
@@ -584,7 +584,7 @@ ENTRY(copyout)
 	ldrne	ip, [r0], #0x04
 	subne	r2, r2, #0x04
 	strtne	ip, [r1], #0x04
-	
+
 	stmfd	sp!, {r4-r9}		/* Free up some registers */
 	mov	r3, #-1			/* Signal restore r4-r9 */
 

Modified: head/sys/arm/arm/blockio.S
==============================================================================
--- head/sys/arm/arm/blockio.S	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/blockio.S	Sun May 24 12:20:11 2015	(r283366)
@@ -43,7 +43,7 @@
  *
  * Created      : 08/10/94
  * Modified	: 22/01/99  -- R.Earnshaw
- *			       Faster, and small tweaks for StrongARM 	
+ *			       Faster, and small tweaks for StrongARM
  */
 
 #include <machine/asm.h>
@@ -251,7 +251,7 @@ ENTRY(outsw)
 
 	str	r3, [r0]
 	str	ip, [r0]
-	
+
 /*	mov	ip, r3, lsl #16
  *	orr	ip, ip, ip, lsr #16
  *	str	ip, [r0]
@@ -358,7 +358,7 @@ ENTRY(outsw16)
 	eor	r3, r3, r4, lsl #16	/* r3 = (A^B^A)(B) = (B)(B) */
 	str	r3, [r0]
 	str	r4, [r0]
-	
+
 /*	mov	r3, r4, lsl #16
  *	orr	r3, r3, r3, lsr #16
  *	str	r3, [r0]

Modified: head/sys/arm/arm/bus_space_base.c
==============================================================================
--- head/sys/arm/arm/bus_space_base.c	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/bus_space_base.c	Sun May 24 12:20:11 2015	(r283366)
@@ -116,10 +116,10 @@ static struct bus_space arm_base_bus_spa
 	.bs_c_8		= BS_UNIMPLEMENTED,
 
 	/* read stream (single) */
-	.bs_r_1_s	= NULL,   /* Use inline code in bus.h */ 
-	.bs_r_2_s	= NULL,   /* Use inline code in bus.h */ 
-	.bs_r_4_s	= NULL,   /* Use inline code in bus.h */ 
-	.bs_r_8_s	= NULL,   /* Use inline code in bus.h */ 
+	.bs_r_1_s	= NULL,   /* Use inline code in bus.h */
+	.bs_r_2_s	= NULL,   /* Use inline code in bus.h */
+	.bs_r_4_s	= NULL,   /* Use inline code in bus.h */
+	.bs_r_8_s	= NULL,   /* Use inline code in bus.h */
 
 	/* read multiple stream */
 	.bs_rm_1_s	= generic_bs_rm_1,
@@ -134,10 +134,10 @@ static struct bus_space arm_base_bus_spa
 	.bs_rr_8_s	= BS_UNIMPLEMENTED,
 
 	/* write stream (single) */
-	.bs_w_1_s	= NULL,   /* Use inline code in bus.h */ 
-	.bs_w_2_s	= NULL,   /* Use inline code in bus.h */ 
-	.bs_w_4_s	= NULL,   /* Use inline code in bus.h */ 
-	.bs_w_8_s	= NULL,   /* Use inline code in bus.h */ 
+	.bs_w_1_s	= NULL,   /* Use inline code in bus.h */
+	.bs_w_2_s	= NULL,   /* Use inline code in bus.h */
+	.bs_w_4_s	= NULL,   /* Use inline code in bus.h */
+	.bs_w_8_s	= NULL,   /* Use inline code in bus.h */
 
 	/* write multiple stream */
 	.bs_wm_1_s	= generic_bs_wm_1,

Modified: head/sys/arm/arm/busdma_machdep-v6.c
==============================================================================
--- head/sys/arm/arm/busdma_machdep-v6.c	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/busdma_machdep-v6.c	Sun May 24 12:20:11 2015	(r283366)
@@ -160,7 +160,7 @@ SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_d
    "Number of active maps for bus_dmamem_alloc buffers");
 SYSCTL_UINT(_hw_busdma, OID_AUTO, maps_coherent, CTLFLAG_RD, &maps_coherent, 0,
    "Number of active maps with BUS_DMA_COHERENT flag set");
-SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_total, CTLFLAG_RD, 
+SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_total, CTLFLAG_RD,
     &maploads_total, "Number of load operations performed");
 SYSCTL_COUNTER_U64(_hw_busdma, OID_AUTO, maploads_bounced, CTLFLAG_RD,
     &maploads_bounced, "Number of load operations that used bounce buffers");
@@ -230,14 +230,14 @@ busdma_init(void *dummy)
 	uma_flags = 0;
 
 	/* Create a cache of buffers in standard (cacheable) memory. */
-	standard_allocator = busdma_bufalloc_create("buffer", 
+	standard_allocator = busdma_bufalloc_create("buffer",
 	    arm_dcache_align,	/* minimum_alignment */
-	    NULL,		/* uma_alloc func */ 
+	    NULL,		/* uma_alloc func */
 	    NULL,		/* uma_free func */
 	    uma_flags);		/* uma_zcreate_flags */
 
 #ifdef INVARIANTS
-	/* 
+	/*
 	 * Force UMA zone to allocate service structures like
 	 * slabs using own allocator. uma_debug code performs
 	 * atomic ops on uma_slab_t fields and safety of this
@@ -251,8 +251,8 @@ busdma_init(void *dummy)
 	 */
 	coherent_allocator = busdma_bufalloc_create("coherent",
 	    arm_dcache_align,	/* minimum_alignment */
-	    busdma_bufalloc_alloc_uncacheable, 
-	    busdma_bufalloc_free_uncacheable, 
+	    busdma_bufalloc_alloc_uncacheable,
+	    busdma_bufalloc_free_uncacheable,
 	    uma_flags);	/* uma_zcreate_flags */
 }
 
@@ -343,7 +343,7 @@ cacheline_bounce(bus_dmamap_t map, bus_a
  * address spaces.
  */
 static __inline int
-might_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t addr, 
+might_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t addr,
     bus_size_t size)
 {
 
@@ -364,7 +364,7 @@ might_bounce(bus_dma_tag_t dmat, bus_dma
  * the DMA needs to bounce, otherwise any DMA within the zone bounces.
  */
 static int
-must_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr, 
+must_bounce(bus_dma_tag_t dmat, bus_dmamap_t map, bus_addr_t paddr,
     bus_size_t size)
 {
 
@@ -387,11 +387,11 @@ must_bounce(bus_dma_tag_t dmat, bus_dmam
 	 */
 	while (dmat != NULL && exclusion_bounce(dmat)) {
 		if ((paddr >= dmat->lowaddr && paddr <= dmat->highaddr) &&
-		    (dmat->filter == NULL || 
+		    (dmat->filter == NULL ||
 		    dmat->filter(dmat->filterarg, paddr) != 0))
 			return (1);
 		dmat = dmat->parent;
-	} 
+	}
 
 	return (0);
 }
@@ -554,7 +554,7 @@ bus_dma_tag_create(bus_dma_tag_t parent,
 		 * number of pages in a transfer.
 		 */
 		maxsize = roundup2(maxsize, PAGE_SIZE) + PAGE_SIZE;
-		
+
 		if ((error = alloc_bounce_zone(newtag)) != 0) {
 			free(newtag, M_DEVBUF);
 			return (error);
@@ -630,7 +630,7 @@ static int allocate_bz_and_pages(bus_dma
 	struct bounce_zone *bz;
 	int maxpages;
 	int error;
-		
+
 	if (dmat->bounce_zone == NULL)
 		if ((error = alloc_bounce_zone(dmat)) != 0)
 			return (error);
@@ -651,13 +651,13 @@ static int allocate_bz_and_pages(bus_dma
 	if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0 ||
 	    (bz->map_count > 0 && bz->total_bpages < maxpages)) {
 		int pages;
-		
+
 		pages = atop(roundup2(dmat->maxsize, PAGE_SIZE)) + 1;
 		pages = MIN(maxpages - bz->total_bpages, pages);
 		pages = MAX(pages, 2);
 		if (alloc_bounce_pages(dmat, pages) < pages)
 			return (ENOMEM);
-		
+
 		if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0)
 			dmat->flags |= BUS_DMA_MIN_ALLOC_COMP;
 	}
@@ -676,7 +676,7 @@ allocate_map(bus_dma_tag_t dmat, int mfl
 	 * variable-sized array of sync_list structures.  Following that
 	 * we allocate enough extra space to hold the array of bus_dma_segments.
 	 */
-	KASSERT(dmat->nsegments <= MAX_DMA_SEGMENTS, 
+	KASSERT(dmat->nsegments <= MAX_DMA_SEGMENTS,
 	   ("cannot allocate %u dma segments (max is %u)",
 	    dmat->nsegments, MAX_DMA_SEGMENTS));
 	segsize = sizeof(struct bus_dma_segment) * dmat->nsegments;
@@ -931,7 +931,7 @@ _bus_dmamap_count_pages(bus_dma_tag_t dm
 			else
 				paddr = pmap_extract(map->pmap, vaddr);
 			if (must_bounce(dmat, map, paddr,
-			    min(vendaddr - vaddr, (PAGE_SIZE - ((vm_offset_t)vaddr & 
+			    min(vendaddr - vaddr, (PAGE_SIZE - ((vm_offset_t)vaddr &
 			    PAGE_MASK)))) != 0) {
 				map->pagesneeded++;
 			}
@@ -1267,7 +1267,7 @@ _bus_dmamap_fix_user(vm_offset_t buf, bu
 	bus_addr_t curaddr;
 	vm_offset_t va;
 
-	/* 
+	/*
 	 * each synclist entry is contained within a single page.
 	 * this would be needed if BUS_DMASYNC_POSTxxxx was implemented
 	 */
@@ -1339,7 +1339,7 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus
 				cpu_dcache_wb_range((vm_offset_t)bpage->vaddr,
 				    bpage->datacount);
 				l2cache_wb_range((vm_offset_t)bpage->vaddr,
-				    (vm_offset_t)bpage->busaddr, 
+				    (vm_offset_t)bpage->busaddr,
 				    bpage->datacount);
 				bpage = STAILQ_NEXT(bpage, links);
 			}
@@ -1387,10 +1387,10 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus
 				startv = bpage->vaddr &~ arm_dcache_align_mask;
 				startp = bpage->busaddr &~ arm_dcache_align_mask;
 				len = bpage->datacount;
-				
+
 				if (startv != bpage->vaddr)
 					len += bpage->vaddr & arm_dcache_align_mask;
-				if (len & arm_dcache_align_mask) 
+				if (len & arm_dcache_align_mask)
 					len = (len -
 					    (len & arm_dcache_align_mask)) +
 					    arm_dcache_align;
@@ -1473,7 +1473,7 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus
 					    sl->busaddr, 1);
 				}
 				cpu_dcache_inv_range(sl->vaddr, sl->datacount);
-				l2cache_inv_range(sl->vaddr, sl->busaddr, 
+				l2cache_inv_range(sl->vaddr, sl->busaddr,
 				    sl->datacount);
 				sl++;
 			}
@@ -1485,7 +1485,7 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus
 		case BUS_DMASYNC_POSTREAD:
 		case BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE:
 			while (sl != end) {
-				l2cache_inv_range(sl->vaddr, sl->busaddr, 
+				l2cache_inv_range(sl->vaddr, sl->busaddr,
 				    sl->datacount);
 				cpu_dcache_inv_range(sl->vaddr, sl->datacount);
 				sl++;

Modified: head/sys/arm/arm/busdma_machdep.c
==============================================================================
--- head/sys/arm/arm/busdma_machdep.c	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/busdma_machdep.c	Sun May 24 12:20:11 2015	(r283366)
@@ -237,7 +237,7 @@ dmamap_ctor(void *mem, int size, void *a
  * This is the dtor function passed to uma_zcreate() for the pool of dma maps.
  * It may need platform-specific changes if this code is copied              .
  */
-static void 
+static void
 dmamap_dtor(void *mem, int size, void *arg)
 {
 	bus_dmamap_t map;
@@ -256,9 +256,9 @@ busdma_init(void *dummy)
 	    dmamap_ctor, dmamap_dtor, NULL, NULL, UMA_ALIGN_PTR, 0);
 
 	/* Create a cache of buffers in standard (cacheable) memory. */
-	standard_allocator = busdma_bufalloc_create("buffer", 
+	standard_allocator = busdma_bufalloc_create("buffer",
 	    arm_dcache_align,	/* minimum_alignment */
-	    NULL,		/* uma_alloc func */ 
+	    NULL,		/* uma_alloc func */
 	    NULL,		/* uma_free func */
 	    0);			/* uma_zcreate_flags */
 
@@ -268,8 +268,8 @@ busdma_init(void *dummy)
 	 */
 	coherent_allocator = busdma_bufalloc_create("coherent",
 	    arm_dcache_align,	/* minimum_alignment */
-	    busdma_bufalloc_alloc_uncacheable, 
-	    busdma_bufalloc_free_uncacheable, 
+	    busdma_bufalloc_alloc_uncacheable,
+	    busdma_bufalloc_free_uncacheable,
 	    0);			/* uma_zcreate_flags */
 }
 
@@ -308,7 +308,7 @@ run_filter(bus_dma_tag_t dmat, bus_addr_
 		  || (*dmat->filter)(dmat->filterarg, paddr) != 0))
 			retval = 1;
 
-		dmat = dmat->parent;		
+		dmat = dmat->parent;
 	} while (retval == 0 && dmat != NULL);
 	return (retval);
 }
@@ -531,13 +531,13 @@ bus_dma_tag_destroy(bus_dma_tag_t dmat)
 #endif
 
 	if (dmat != NULL) {
-		
+
                 if (dmat->map_count != 0)
                         return (EBUSY);
-		
+
                 while (dmat != NULL) {
                         bus_dma_tag_t parent;
-			
+
                         parent = dmat->parent;
                         atomic_subtract_int(&dmat->ref_count, 1);
                         if (dmat->ref_count == 0) {
@@ -588,7 +588,7 @@ bus_dmamap_create(bus_dma_tag_t dmat, in
 	 * now, because we can't sleep for resources at map load time.
 	 */
 	if (dmat->segments == NULL) {
-		dmat->segments = malloc(dmat->nsegments * 
+		dmat->segments = malloc(dmat->nsegments *
 		    sizeof(*dmat->segments), M_DEVBUF, M_NOWAIT);
 		if (dmat->segments == NULL) {
 			free(slist, M_DEVBUF);
@@ -701,7 +701,7 @@ bus_dmamem_alloc(bus_dma_tag_t dmat, voi
 	 * now, because we can't sleep for resources at map load time.
 	 */
 	if (dmat->segments == NULL)
-		dmat->segments = malloc(dmat->nsegments * 
+		dmat->segments = malloc(dmat->nsegments *
 		   sizeof(*dmat->segments), M_DEVBUF, mflags);
 
 	slist = malloc(sizeof(*slist) * dmat->nsegments, M_DEVBUF, M_NOWAIT);
@@ -918,7 +918,7 @@ _bus_dmamap_addseg(bus_dma_tag_t dmat, b
 		 * memory address to an address in the DMA window.
 		 */
 		curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase;
-					
+
 	}
 
 	seg = *segp;
@@ -1206,7 +1206,7 @@ _bus_dmamap_sync_bp(bus_dma_tag_t dmat, 
 	STAILQ_FOREACH(bpage, &map->bpages, links) {
 		if (op & BUS_DMASYNC_PREWRITE) {
 			if (bpage->datavaddr != 0)
-				bcopy((void *)bpage->datavaddr, 
+				bcopy((void *)bpage->datavaddr,
 				    (void *)bpage->vaddr, bpage->datacount);
 			else
 				physcopyout(bpage->dataaddr,

Modified: head/sys/arm/arm/copystr.S
==============================================================================
--- head/sys/arm/arm/copystr.S	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/copystr.S	Sun May 24 12:20:11 2015	(r283366)
@@ -38,7 +38,6 @@
  * Created      : 16/05/95
  */
 
-	
 #include "assym.s"
 #include <machine/asm.h>
 #include <machine/armreg.h>

Modified: head/sys/arm/arm/cpu_asm-v6.S
==============================================================================
--- head/sys/arm/arm/cpu_asm-v6.S	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/cpu_asm-v6.S	Sun May 24 12:20:11 2015	(r283366)
@@ -33,10 +33,10 @@
 #include <machine/armreg.h>
 #include <machine/sysreg.h>
 
-/* 
+/*
  * Define cache functions used by startup code, which counts on the fact that
  * only r0-r3,r12 (ip) are modified and no stack space is used.  These functions
- * must be called with interrupts disabled.  Moreover, these work only with 
+ * must be called with interrupts disabled.  Moreover, these work only with
  * caches integrated to CPU (accessible via CP15); systems with an external L2
  * cache controller such as a PL310 need separate calls to that device driver
  * to affect L2 caches.  This is not a factor during early kernel startup, as

Modified: head/sys/arm/arm/cpufunc.c
==============================================================================
--- head/sys/arm/arm/cpufunc.c	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/cpufunc.c	Sun May 24 12:20:11 2015	(r283366)
@@ -361,7 +361,7 @@ struct cpu_functions pj4bv7_cpufuncs = {
 
 struct cpu_functions xscale_cpufuncs = {
 	/* CPU functions */
-	
+
 	cpufunc_id,			/* id			*/
 	xscale_cpwait,			/* cpwait		*/
 
@@ -426,7 +426,7 @@ struct cpu_functions xscale_cpufuncs = {
 #ifdef CPU_XSCALE_81342
 struct cpu_functions xscalec3_cpufuncs = {
 	/* CPU functions */
-	
+
 	cpufunc_id,			/* id			*/
 	xscale_cpwait,			/* cpwait		*/
 
@@ -553,63 +553,63 @@ struct cpu_functions fa526_cpufuncs = {
 #if defined(CPU_ARM1176)
 struct cpu_functions arm1176_cpufuncs = {
 	/* CPU functions */
-	
+
 	cpufunc_id,                     /* id                   */
 	cpufunc_nullop,                 /* cpwait               */
-	
+
 	/* MMU functions */
-	
+
 	cpufunc_control,                /* control              */
 	cpufunc_domains,                /* Domain               */
 	arm11x6_setttb,                 /* Setttb               */
 	cpufunc_faultstatus,            /* Faultstatus          */
 	cpufunc_faultaddress,           /* Faultaddress         */
-	
+
 	/* TLB functions */
-	
+
 	arm11_tlb_flushID,              /* tlb_flushID          */
 	arm11_tlb_flushID_SE,           /* tlb_flushID_SE       */
 	arm11_tlb_flushI,               /* tlb_flushI           */
 	arm11_tlb_flushI_SE,            /* tlb_flushI_SE        */
 	arm11_tlb_flushD,               /* tlb_flushD           */
 	arm11_tlb_flushD_SE,            /* tlb_flushD_SE        */
-	
+
 	/* Cache operations */
-	
+
 	arm11x6_icache_sync_all,        /* icache_sync_all      */
 	arm11x6_icache_sync_range,      /* icache_sync_range    */
-	
+
 	arm11x6_dcache_wbinv_all,       /* dcache_wbinv_all     */
 	armv6_dcache_wbinv_range,       /* dcache_wbinv_range   */
 	armv6_dcache_inv_range,         /* dcache_inv_range     */
 	armv6_dcache_wb_range,          /* dcache_wb_range      */
-	
+
 	armv6_idcache_inv_all,		/* idcache_inv_all	*/
 	arm11x6_idcache_wbinv_all,      /* idcache_wbinv_all    */
 	arm11x6_idcache_wbinv_range,    /* idcache_wbinv_range  */
-	
+
 	(void *)cpufunc_nullop,         /* l2cache_wbinv_all    */
 	(void *)cpufunc_nullop,         /* l2cache_wbinv_range  */
 	(void *)cpufunc_nullop,         /* l2cache_inv_range    */
 	(void *)cpufunc_nullop,         /* l2cache_wb_range     */
 	(void *)cpufunc_nullop,         /* l2cache_drain_writebuf */
-	
+
 	/* Other functions */
-	
+
 	arm11x6_flush_prefetchbuf,      /* flush_prefetchbuf    */
 	arm11_drain_writebuf,           /* drain_writebuf       */
 	cpufunc_nullop,                 /* flush_brnchtgt_C     */
 	(void *)cpufunc_nullop,         /* flush_brnchtgt_E     */
-	
+
 	arm11x6_sleep,                  /* sleep                */
-	
+
 	/* Soft functions */
-	
+
 	cpufunc_null_fixup,             /* dataabt_fixup        */
 	cpufunc_null_fixup,             /* prefetchabt_fixup    */
-	
+
 	arm11_context_switch,           /* context_switch       */
-	
+
 	arm11x6_setup                   /* cpu setup            */
 };
 #endif /*CPU_ARM1176 */
@@ -617,46 +617,46 @@ struct cpu_functions arm1176_cpufuncs = 
 #if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
 struct cpu_functions cortexa_cpufuncs = {
 	/* CPU functions */
-	
+
 	cpufunc_id,                     /* id                   */
 	cpufunc_nullop,                 /* cpwait               */
-	
+
 	/* MMU functions */
-	
+
 	cpufunc_control,                /* control              */
 	cpufunc_domains,                /* Domain               */
 	armv7_setttb,                   /* Setttb               */
 	cpufunc_faultstatus,            /* Faultstatus          */
 	cpufunc_faultaddress,           /* Faultaddress         */
-	
-	/* 
+
+	/*
 	 * TLB functions.  ARMv7 does all TLB ops based on a unified TLB model
 	 * whether the hardware implements separate I+D or not, so we use the
 	 * same 'ID' functions for all 3 variations.
 	 */
-	
+
 	armv7_tlb_flushID,              /* tlb_flushID          */
 	armv7_tlb_flushID_SE,           /* tlb_flushID_SE       */
 	armv7_tlb_flushID,              /* tlb_flushI           */
 	armv7_tlb_flushID_SE,           /* tlb_flushI_SE        */
 	armv7_tlb_flushID,              /* tlb_flushD           */
 	armv7_tlb_flushID_SE,           /* tlb_flushD_SE        */
-	
+
 	/* Cache operations */
-	
+
 	armv7_icache_sync_all, 	        /* icache_sync_all      */
 	armv7_icache_sync_range,        /* icache_sync_range    */
-	
+
 	armv7_dcache_wbinv_all,         /* dcache_wbinv_all     */
 	armv7_dcache_wbinv_range,       /* dcache_wbinv_range   */
 	armv7_dcache_inv_range,         /* dcache_inv_range     */
 	armv7_dcache_wb_range,          /* dcache_wb_range      */
-	
+
 	armv7_idcache_inv_all,		/* idcache_inv_all	*/
 	armv7_idcache_wbinv_all,        /* idcache_wbinv_all    */
 	armv7_idcache_wbinv_range,      /* idcache_wbinv_range  */
-	
-	/* 
+
+	/*
 	 * Note: For CPUs using the PL310 the L2 ops are filled in when the
 	 * L2 cache controller is actually enabled.
 	 */
@@ -665,23 +665,23 @@ struct cpu_functions cortexa_cpufuncs = 
 	(void *)cpufunc_nullop,         /* l2cache_inv_range    */
 	(void *)cpufunc_nullop,         /* l2cache_wb_range     */
 	(void *)cpufunc_nullop,         /* l2cache_drain_writebuf */
-	
+
 	/* Other functions */
-	
+
 	cpufunc_nullop,                 /* flush_prefetchbuf    */
 	armv7_drain_writebuf,           /* drain_writebuf       */
 	cpufunc_nullop,                 /* flush_brnchtgt_C     */
 	(void *)cpufunc_nullop,         /* flush_brnchtgt_E     */
-	
+
 	armv7_cpu_sleep,                /* sleep                */
-	
+
 	/* Soft functions */
-	
+
 	cpufunc_null_fixup,             /* dataabt_fixup        */
 	cpufunc_null_fixup,             /* prefetchabt_fixup    */
-	
+
 	armv7_context_switch,           /* context_switch       */
-	
+
 	cortexa_setup                     /* cpu setup            */
 };
 #endif /* CPU_CORTEXA */
@@ -758,7 +758,7 @@ get_cachetype_cp15()
 				__asm __volatile("mrc p15, 1, %0, c0, c0, 0"
 				    : "=r" (csize));
 				arm_cache_type[sel] = csize;
-				arm_dcache_align = 1 << 
+				arm_dcache_align = 1 <<
 				    (CPUV7_CT_xSIZE_LEN(csize) + 4);
 				arm_dcache_align_mask = arm_dcache_align - 1;
 			}
@@ -913,12 +913,12 @@ set_cpufuncs()
 		cpufuncs = cortexa_cpufuncs;
 		cpu_reset_needs_v4_MMU_disable = 1;     /* V4 or higher */
 		get_cachetype_cp15();
-		
+
 		pmap_pte_init_mmu_v6();
 		goto out;
 	}
 #endif /* CPU_CORTEXA */
-		
+
 #if defined(CPU_MV_PJ4B)
 	if (cputype == CPU_ID_MV88SV581X_V7 ||
 	    cputype == CPU_ID_MV88SV584X_V7 ||
@@ -1165,7 +1165,7 @@ arm11x6_setup(void)
 		(3 << 30) | /* SBZ */
 		(1 << 29) | /* FA */
 		(1 << 28) | /* TR */
-		(3 << 26) | /* SBZ */ 
+		(3 << 26) | /* SBZ */
 		(3 << 19) | /* SBZ */
 		(1 << 17);  /* SBZ */
 
@@ -1258,39 +1258,39 @@ void
 cortexa_setup(void)
 {
 	int cpuctrl, cpuctrlmask;
-	
+
 	cpuctrlmask = CPU_CONTROL_MMU_ENABLE |     /* MMU enable         [0] */
 	    CPU_CONTROL_AFLT_ENABLE |    /* Alignment fault    [1] */
 	    CPU_CONTROL_DC_ENABLE |      /* DCache enable      [2] */
 	    CPU_CONTROL_BPRD_ENABLE |    /* Branch prediction [11] */
 	    CPU_CONTROL_IC_ENABLE |      /* ICache enable     [12] */
 	    CPU_CONTROL_VECRELOC;        /* Vector relocation [13] */
-	
+
 	cpuctrl = CPU_CONTROL_MMU_ENABLE |
 	    CPU_CONTROL_IC_ENABLE |
 	    CPU_CONTROL_DC_ENABLE |
 	    CPU_CONTROL_BPRD_ENABLE;
-	
+
 #ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
 	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
 #endif
-	
+
 	/* Switch to big endian */
 #ifdef __ARMEB__
 	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
 #endif
-	
+
 	/* Check if the vector page is at the high address (0xffff0000) */
 	if (vector_page == ARM_VECTORS_HIGH)
 		cpuctrl |= CPU_CONTROL_VECRELOC;
-	
+
 	/* Clear out the cache */
 	cpu_idcache_wbinv_all();
-	
+
 	/* Set the control register */
 	ctrl = cpuctrl;
 	cpu_control(cpuctrlmask, cpuctrl);
-	
+
 	/* And again. */
 	cpu_idcache_wbinv_all();
 #ifdef SMP

Modified: head/sys/arm/arm/cpufunc_asm_arm11x6.S
==============================================================================
--- head/sys/arm/arm/cpufunc_asm_arm11x6.S	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/cpufunc_asm_arm11x6.S	Sun May 24 12:20:11 2015	(r283366)
@@ -73,7 +73,7 @@ __FBSDID("$FreeBSD$");
  *
  *    Erratum 411920 in ARM1136 (fixed in r1p4)
  *    Erratum 415045 in ARM1176 (fixed in r0p5?)
- * 
+ *
  *	- value of arg 'reg' Should Be Zero
  */
 #define Invalidate_I_cache(Rtmp1, Rtmp2) \
@@ -150,20 +150,20 @@ ENTRY_NP(arm11x6_icache_sync_range)
 	/* Erratum ARM1176 371367 */
 	mrs	r2, cpsr		/* save the CPSR */
 	cpsid	ifa			/* disable interrupts (irq,fiq,abort) */
-	mov	r3, #0 
+	mov	r3, #0
 	mcr	p15, 0, r3, c13, c0, 0	/* write FCSE (uTLB invalidate) */
 	mcr	p15, 0, r3, c7, c5, 4	/* flush prefetch buffer */
-	add	r3, pc, #0x24 
+	add	r3, pc, #0x24
 	mcr	p15, 0, r3, c7, c13, 1	/* prefetch I-cache line */
 	mcrr	p15, 0, r1, r0, c5	/* invalidate I-cache range */
 	msr	cpsr_cx, r2		/* local_irq_restore */
-	nop 
-	nop 
-	nop 
-	nop 
-	nop 
-	nop 
-	nop 
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
 
 	mcrr	p15, 0, r1, r0, c12	/* clean and invalidate D cache range */ /* XXXNH */
 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
@@ -177,20 +177,20 @@ ENTRY_NP(arm11x6_idcache_wbinv_range)
 	/* Erratum ARM1176 371367 */
 	mrs	r2, cpsr		/* save the CPSR */
 	cpsid	ifa			/* disable interrupts (irq,fiq,abort) */
-	mov	r3, #0 
+	mov	r3, #0
 	mcr	p15, 0, r3, c13, c0, 0	/* write FCSE (uTLB invalidate) */
 	mcr	p15, 0, r3, c7, c5, 4	/* flush prefetch buffer */
-	add	r3, pc, #0x24 
+	add	r3, pc, #0x24
 	mcr	p15, 0, r3, c7, c13, 1	/* prefetch I-cache line */
 	mcrr	p15, 0, r1, r0, c5	/* invalidate I-cache range */
 	msr	cpsr_cx, r2		/* local_irq_restore */
-	nop 
-	nop 
-	nop 
-	nop 
-	nop 
-	nop 
-	nop 
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
 
 	mcrr	p15, 0, r1, r0, c14	/* clean and invalidate D cache range */
 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
@@ -199,7 +199,7 @@ END(arm11x6_idcache_wbinv_range)
 
 /*
  * Preload the cache before issuing the WFI by conditionally disabling the
- * mcr intstructions the first time around the loop. Ensure the function is 
+ * mcr intstructions the first time around the loop. Ensure the function is
  * cacheline aligned.
  */
 	.arch	armv6

Modified: head/sys/arm/arm/cpufunc_asm_arm9.S
==============================================================================
--- head/sys/arm/arm/cpufunc_asm_arm9.S	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/cpufunc_asm_arm9.S	Sun May 24 12:20:11 2015	(r283366)
@@ -130,7 +130,7 @@ ENTRY(arm9_dcache_wb_range)
 	bhi	.Larm9_wb_next
 	mov	pc, lr
 END(arm9_dcache_wb_range)
-	
+
 ENTRY(arm9_dcache_wbinv_range)
 	ldr	ip, .Larm9_line_size
 	cmp	r1, #0x4000
@@ -147,7 +147,7 @@ ENTRY(arm9_dcache_wbinv_range)
 	bhi	.Larm9_wbinv_next
 	mov	pc, lr
 END(arm9_dcache_wbinv_range)
-	
+
 /*
  * Note, we must not invalidate everything.  If the range is too big we
  * must use wb-inv of the entire cache.

Modified: head/sys/arm/arm/cpufunc_asm_armv6.S
==============================================================================
--- head/sys/arm/arm/cpufunc_asm_armv6.S	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/cpufunc_asm_armv6.S	Sun May 24 12:20:11 2015	(r283366)
@@ -37,7 +37,7 @@
 /*
  * $FreeBSD$
  */
- 
+
 #include <machine/asm.h>
 
 	.arch	armv6
@@ -69,7 +69,7 @@ ENTRY(armv6_dcache_wb_range)
 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
 	RET
 END(armv6_dcache_wb_range)
-	
+
 /* LINTSTUB: void armv6_dcache_wbinv_range(vaddr_t, vsize_t); */
 ENTRY(armv6_dcache_wbinv_range)
 	add	r1, r1, r0
@@ -78,7 +78,7 @@ ENTRY(armv6_dcache_wbinv_range)
 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
 	RET
 END(armv6_dcache_wbinv_range)
-	
+
 /*
  * Note, we must not invalidate everything.  If the range is too big we
  * must use wb-inv of the entire cache.

Modified: head/sys/arm/arm/cpufunc_asm_armv7.S
==============================================================================
--- head/sys/arm/arm/cpufunc_asm_armv7.S	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/cpufunc_asm_armv7.S	Sun May 24 12:20:11 2015	(r283366)
@@ -64,7 +64,7 @@ __FBSDID("$FreeBSD$");
 #define PT_OUTER_WT	(2 << 3)
 #define PT_OUTER_WB	(3 << 3)
 #define PT_OUTER_WBWA	(1 << 3)
-	
+
 #ifdef SMP
 #define PT_ATTR	(PT_S|PT_INNER_WBWA|PT_OUTER_WBWA|PT_NOS)
 #else

Modified: head/sys/arm/arm/cpufunc_asm_xscale_c3.S
==============================================================================
--- head/sys/arm/arm/cpufunc_asm_xscale_c3.S	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/cpufunc_asm_xscale_c3.S	Sun May 24 12:20:11 2015	(r283366)
@@ -135,7 +135,7 @@ __FBSDID("$FreeBSD$");
 	ldr	r4, .Lblock_userspace_access			;	\
 	ldr	ip, [r4]					;	\
 	orr	r0, ip, #1					;	\
-	str	r0, [r4]	
+	str	r0, [r4]
 
 #define	XSCALE_CACHE_CLEAN_UNBLOCK					\
 	str	ip, [r3]					;	\
@@ -217,7 +217,7 @@ ENTRY(xscalec3_cache_syncI_rng)
 
 	CPWAIT_AND_RETURN(r0)
 END(xscalec3_cache_syncI_rng)
-	
+
 ENTRY(xscalec3_cache_purgeD_rng)
 
 	cmp	r1, #0x4000

Modified: head/sys/arm/arm/cpuinfo.c
==============================================================================
--- head/sys/arm/arm/cpuinfo.c	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/cpuinfo.c	Sun May 24 12:20:11 2015	(r283366)
@@ -48,7 +48,7 @@ void
 cpuinfo_init(void)
 {
 
-	cpuinfo.midr = cp15_midr_get();	
+	cpuinfo.midr = cp15_midr_get();
 	/* Test old version id schemes first */
 	if ((cpuinfo.midr & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) {
 		if (CPU_ID_ISOLD(cpuinfo.midr)) {
@@ -74,7 +74,7 @@ cpuinfo_init(void)
 		/* non ARM -> must be new id scheme */
 		cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F;
 		cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F;
-	}	
+	}
 	/* Parse rest of MIDR  */
 	cpuinfo.implementer = (cpuinfo.midr >> 24) & 0xFF;
 	cpuinfo.part_number = (cpuinfo.midr >> 4) & 0xFFF;
@@ -86,11 +86,11 @@ cpuinfo_init(void)
 	cpuinfo.tlbtr = cp15_tlbtr_get();
 	cpuinfo.mpidr = cp15_mpidr_get();
 	cpuinfo.revidr = cp15_revidr_get();
-		
+
 	/* if CPU is not v7 cpu id scheme */
 	if (cpuinfo.architecture != 0xF)
 		return;
-		
+
 	cpuinfo.id_pfr0 = cp15_id_pfr0_get();
 	cpuinfo.id_pfr1 = cp15_id_pfr1_get();
 	cpuinfo.id_dfr0 = cp15_id_dfr0_get();

Modified: head/sys/arm/arm/db_interface.c
==============================================================================
--- head/sys/arm/arm/db_interface.c	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/db_interface.c	Sun May 24 12:20:11 2015	(r283366)
@@ -326,12 +326,9 @@ branch_taken(u_int insn, db_addr_t pc)
 				default:
 					break; /* XXX */
 				}
-					
 			}
 			return (addr + offset);
-				
 		}
-		
 	case 0xa:	/* b ... */
 	case 0xb:	/* bl ... */
 		addr = ((insn << 2) & 0x03ffffff);

Modified: head/sys/arm/arm/elf_trampoline.c
==============================================================================
--- head/sys/arm/arm/elf_trampoline.c	Sun May 24 12:12:01 2015	(r283365)
+++ head/sys/arm/arm/elf_trampoline.c	Sun May 24 12:20:11 2015	(r283366)
@@ -93,7 +93,7 @@ extern void sheeva_l2cache_wbinv_all(voi
 #define cpu_idcache_wbinv_all	armv7_idcache_wbinv_all
 #define cpu_l2cache_wbinv_all()
 #else
-#define cpu_l2cache_wbinv_all()	
+#define cpu_l2cache_wbinv_all()
 #endif
 
 static void armadaxp_idcache_wbinv_all(void);
@@ -216,7 +216,7 @@ _startC(void)
 		    "mov sp, %1\n"
 		    "mov pc, %0\n"
 		    : : "r" (target_addr), "r" (tmp_sp));
-		
+
 	}
 #endif
 #ifdef KZIP
@@ -225,7 +225,7 @@ _startC(void)
 	sp += 2 * L1_TABLE_SIZE;
 #endif
 	sp += 1024 * 1024; /* Should be enough for a stack */
-	
+
 	__asm __volatile("adr %0, 2f\n"
 	    		 "bic %0, %0, #0xff000000\n"
 			 "and %1, %1, #0xff000000\n"
@@ -366,7 +366,7 @@ get_cachetype_cp15()
 static void
 arm9_setup(void)
 {
-	
+
 	get_cachetype_cp15();
 	arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
 	arm9_dcache_sets_max = (1U << (arm_dcache_l2_linesize +
@@ -490,7 +490,7 @@ load_kernel(unsigned int kstart, unsigne
 	vm_offset_t lastaddr = 0;
 	Elf_Addr ssym = 0;
 	Elf_Dyn *dp;
-	
+
 	eh = (Elf32_Ehdr *)kstart;
 	ssym = 0;
 	entry_point = (void*)eh->e_entry;
@@ -504,7 +504,7 @@ load_kernel(unsigned int kstart, unsigne
 			lastaddr = phdr[i].p_vaddr - KERNVIRTADDR +
 			    curaddr + phdr[i].p_memsz;
 	}
-	
+
 	/* Save the symbol tables, as there're about to be scratched. */
 	memcpy(shdr, (void *)(kstart + eh->e_shoff),
 	    sizeof(*shdr) * eh->e_shnum);
@@ -552,12 +552,12 @@ load_kernel(unsigned int kstart, unsigne
 				lastaddr = roundup(lastaddr,
 				    sizeof(shdr[symstrindex].sh_size));
 			}
-			
+
 		}
 	}
 	if (!d)
 		return ((void *)lastaddr);
-	
+
 	j = eh->e_phnum;
 	for (i = 0; i < j; i++) {
 		volatile char c;
@@ -610,7 +610,7 @@ load_kernel(unsigned int kstart, unsigne
 	((void(*)(void))(entry_point - KERNVIRTADDR + curaddr))();
 	__asm __volatile(".globl func_end\n"
 	    "func_end:");
-	
+
 	/* NOTREACHED */
 	return NULL;
 }
@@ -653,7 +653,7 @@ setup_pagetables(unsigned int pt_addr, v
 			 "mov r0, r0\n"
 			 "sub pc, pc, #4\n" :
 			 "=r" (tmp) : "r" (pd), "r" (domain));
-	
+
 	/*
 	 * XXX: This is the most stupid workaround I've ever wrote.
 	 * For some reason, the KB9202 won't boot the kernel unless
@@ -680,7 +680,7 @@ __start(void)
 	if (*kernel == 0x1f && kernel[1] == 0x8b) {
 		pt_addr = (((int)&_end + KERNSIZE + 0x100) &
 		    ~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE;
-		
+
 #ifdef CPU_ARM9
 		/* So that idcache_wbinv works; */
 		if ((cpufunc_id() & 0x0000f000) == 0x00009000)
@@ -715,7 +715,7 @@ __start(void)
 	dst = (void *)(((vm_offset_t)dst & ~3));
 	pt_addr = ((unsigned int)dst &~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE;
 	setup_pagetables(pt_addr, (vm_paddr_t)curaddr,
-	    (vm_paddr_t)curaddr + 0x10000000, 0);	
+	    (vm_paddr_t)curaddr + 0x10000000, 0);

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



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