From owner-freebsd-arch@FreeBSD.ORG Tue Mar 16 09:21:10 2004 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id B48A916A4E4 for ; Tue, 16 Mar 2004 09:21:10 -0800 (PST) Received: from mail3.speakeasy.net (mail3.speakeasy.net [216.254.0.203]) by mx1.FreeBSD.org (Postfix) with ESMTP id 8C0EB43D39 for ; Tue, 16 Mar 2004 09:21:10 -0800 (PST) (envelope-from jhb@FreeBSD.org) Received: (qmail 16648 invoked from network); 16 Mar 2004 17:21:09 -0000 Received: from dsl027-160-063.atl1.dsl.speakeasy.net (HELO server.baldwin.cx) ([216.27.160.63]) (envelope-sender ) encrypted SMTP for ; 16 Mar 2004 17:21:09 -0000 Received: from 10.50.40.205 (gw1.twc.weather.com [216.133.140.1]) by server.baldwin.cx (8.12.10/8.12.10) with ESMTP id i2GHL528065517; Tue, 16 Mar 2004 12:21:05 -0500 (EST) (envelope-from jhb@FreeBSD.org) From: John Baldwin To: Bosko Milekic Date: Tue, 16 Mar 2004 12:14:56 -0500 User-Agent: KMail/1.6 References: <1077137806.28133.10.camel@herring.nlsystems.com> <200403161012.09174.john@baldwin.cx> <20040316163359.GA7365@technokratis.com> In-Reply-To: <20040316163359.GA7365@technokratis.com> MIME-Version: 1.0 Content-Disposition: inline Message-Id: <200403161214.31276.john@baldwin.cx> Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Spam-Checker-Version: SpamAssassin 2.63 (2004-01-11) on server.baldwin.cx cc: arch@freebsd.org cc: freebsd-arch@freebsd.org Subject: Re: Read Copy Update X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Mar 2004 17:21:10 -0000 On Tuesday 16 March 2004 11:33 am, Bosko Milekic wrote: > On Tue, Mar 16, 2004 at 10:12:09AM -0500, John Baldwin wrote: > > > I was imagining a a pcpu flag which was a 'soft cli', i.e. if a cpu > > > fields an interrupt and the soft cli flag is set, it just clears the > > > interrupt flag in the trapframe and returns. It all works out the same > > > in the end. > > No because if you're in the middle of modifying a pcpu flag and you > take an interrupt you may get scheduled over to another CPU. You > would also have to temporarily pin down the thread to the current CPU > unless you do it with an in-thread flag. > > By the way, the point of all this is that with a combination of > soft-disables and short-term scheduler pinning we should be able to > take the common memory allocation case in UMA out of any lock > requirements (lockless in common case). > > > I have this partly implemented, but because the VM86 code really sucks > > (it just always enables interrupts) the invariants checks I have don't > > make it to single user mode. I haven't decided what to do about VM86 > > yet, and I also haven't handled the problem of switching away from > > interrupt context (for ithread preemption) and switching back and making > > that all work correctly w/o possibly dropping interrupts. > > Do you have your current changes in a separate p4 repo somewhere? The jhb_acpipci_crit branch. Like I said, though, it doesn't boot. There are lots of implementation notes in //depot/user/jhb/acpicpi_crit/notes. -- John Baldwin <>< http://www.baldwin.cx/~john/ "Power Users Use the Power to Serve" = http://www.FreeBSD.org