From owner-dev-commits-src-all@freebsd.org Fri Dec 25 21:06:51 2020 Return-Path: Delivered-To: dev-commits-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id BEAFE4C9AF5; Fri, 25 Dec 2020 21:06:51 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4D2fdR4MgLz3syX; Fri, 25 Dec 2020 21:06:51 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 842361191; Fri, 25 Dec 2020 21:06:51 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 0BPL6prw064266; Fri, 25 Dec 2020 21:06:51 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 0BPL6p4k064265; Fri, 25 Dec 2020 21:06:51 GMT (envelope-from git) Date: Fri, 25 Dec 2020 21:06:51 GMT Message-Id: <202012252106.0BPL6p4k064265@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Brandon Bergren Subject: git: 2ca7f72fee3c - MFC r364447: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: bdragon X-Git-Repository: src X-Git-Refname: refs/heads/stable/12 X-Git-Reftype: branch X-Git-Commit: 2ca7f72fee3cffa0cc366c1db69199b436f2e908 Auto-Submitted: auto-generated X-BeenThere: dev-commits-src-all@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: "Commit messages for all branches of the src repository." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Dec 2020 21:06:51 -0000 The branch stable/12 has been updated by bdragon: URL: https://cgit.FreeBSD.org/src/commit/?id=2ca7f72fee3cffa0cc366c1db69199b436f2e908 commit 2ca7f72fee3cffa0cc366c1db69199b436f2e908 Author: Brandon Bergren AuthorDate: 2020-08-21 03:31:01 +0000 Commit: Brandon Bergren CommitDate: 2020-12-25 21:00:51 +0000 MFC r364447: [PowerPC] Fix translation-related crashes during startup After spending a lot of time trying to track down what was going on, I have isolated the "black screen" failures when using boot1 to boot a G4 machine. It turns out we were replacing the traps before installing the temporary BAT entry for the bottom of physical memory. That meant that until the MMU was bootstrapped, the cached translations were the only thing keeping us from losing. Throwing boot1 into the mix was affecting execution flow enough to cause us to hit an uncached page and crash. Fix this by properly setting up the initial BAT entry at the same time we are replacing the OpenFirmware traps, so we can continue executing in segment 0 until the rest of the DMAP has been set up. A second thing discovered while researching this is that we were entering a BAT region for segment 16. It turns out this range was a) considered part of KVA, and b) has firmware mappings with varying attributes. If we ever accessed an unmapped page in segment 16, it would cause a BAT entry to be installed for the whole segment, which would bypass the existing mappings until it was flushed out again. Instead, translate the OFW memory attributes into VM memory attributes and install the ranges into the kernel address space properly. Reviewed by: adalava MFC after: 3 weeks Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D25547 (cherry picked from commit f10baa404986adb5733fd5745d467a8f69409ce3) --- sys/powerpc/aim/aim_machdep.c | 19 ++++++++++++ sys/powerpc/aim/mmu_oea.c | 67 ++++++++++++++++++++++++------------------- 2 files changed, 57 insertions(+), 29 deletions(-) diff --git a/sys/powerpc/aim/aim_machdep.c b/sys/powerpc/aim/aim_machdep.c index 6d84798ee21d..aff409d3ccc5 100644 --- a/sys/powerpc/aim/aim_machdep.c +++ b/sys/powerpc/aim/aim_machdep.c @@ -361,6 +361,25 @@ aim_cpu_init(vm_offset_t toc) bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset); bcopy(&restorebridge, (void *)EXC_TRC, trap_offset); bcopy(&restorebridge, (void *)EXC_BPT, trap_offset); + } else { + + /* + * Use an IBAT and a DBAT to map the bottom 256M segment. + * + * It is very important to do it *now* to avoid taking a + * fault in .text / .data before the MMU is bootstrapped, + * because until then, the translation data has not been + * copied over from OpenFirmware, so our DSI/ISI will fail + * to find a match. + */ + + battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); + battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); + + __asm (".balign 32; \n" + "mtibatu 0,%0; mtibatl 0,%1; isync; \n" + "mtdbatu 0,%0; mtdbatl 0,%1; isync" + :: "r"(battable[0].batu), "r"(battable[0].batl)); } #else trapsize = (size_t)&hypertrapcodeend - (size_t)&hypertrapcode; diff --git a/sys/powerpc/aim/mmu_oea.c b/sys/powerpc/aim/mmu_oea.c index 187a96d4e90a..03e8218c187e 100644 --- a/sys/powerpc/aim/mmu_oea.c +++ b/sys/powerpc/aim/mmu_oea.c @@ -420,6 +420,32 @@ moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma) return pte_lo; } +/* + * Translate OFW translations into VM attributes. + */ +static __inline vm_memattr_t +moea_bootstrap_convert_wimg(uint32_t mode) +{ + + switch (mode) { + case (PTE_I | PTE_G): + /* PCI device memory */ + return VM_MEMATTR_UNCACHEABLE; + case (PTE_M): + /* Explicitly coherent */ + return VM_MEMATTR_CACHEABLE; + case 0: /* Default claim */ + case 2: /* Alternate PP bits set by OF for the original payload */ + /* "Normal" memory. */ + return VM_MEMATTR_DEFAULT; + + default: + /* Err on the side of caution for unknowns */ + /* XXX should we panic instead? */ + return VM_MEMATTR_UNCACHEABLE; + } +} + static void tlbie(vm_offset_t va) { @@ -670,13 +696,6 @@ moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) vm_size_t size, physsz, hwphyssz; vm_offset_t pa, va, off; void *dpcpu; - register_t msr; - - /* - * Set up BAT0 to map the lowest 256 MB area - */ - battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW); - battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs); /* * Map PCI memory space. @@ -693,24 +712,7 @@ moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW); battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs); - /* - * Map obio devices. - */ - battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW); - battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs); - - /* - * Use an IBAT and a DBAT to map the bottom segment of memory - * where we are. Turn off instruction relocation temporarily - * to prevent faults while reprogramming the IBAT. - */ - msr = mfmsr(); - mtmsr(msr & ~PSL_IR); - __asm (".balign 32; \n" - "mtibatu 0,%0; mtibatl 0,%1; isync; \n" - "mtdbatu 0,%0; mtdbatl 0,%1; isync" - :: "r"(battable[0].batu), "r"(battable[0].batl)); - mtmsr(msr); + powerpc_sync(); /* map pci space */ __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu)); @@ -910,15 +912,22 @@ moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend) /* * If the mapping is 1:1, let the RAM and device * on-demand BAT tables take care of the translation. + * + * However, always enter mappings for segment 16, + * which is mixed-protection and therefore not + * compatible with a BAT entry. */ - if (translations[i].om_va == translations[i].om_pa) - continue; + if ((translations[i].om_va >> ADDR_SR_SHFT) != 0xf && + translations[i].om_va == translations[i].om_pa) + continue; /* Enter the pages */ for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) - moea_kenter(mmup, translations[i].om_va + off, - translations[i].om_pa + off); + moea_kenter_attr(mmup, + translations[i].om_va + off, + translations[i].om_pa + off, + moea_bootstrap_convert_wimg(translations[i].om_mode)); } }