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From: "Justin T. Gibbs" <gibbs@FreeBSD.org>
Date: Fri, 7 Jan 2000 15:08:21 -0800 (PST)
To: cvs-committers@FreeBSD.org, cvs-all@FreeBSD.org
Subject: cvs commit: src/sys/pci ahc_pci.c src/sys/dev/aic7xxx 93cx6.c
         aic7xxx.c aic7xxx.h aic7xxx.reg aic7xxx.seq
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gibbs       2000/01/07 15:08:21 PST

  Modified files:
    sys/pci              ahc_pci.c 
  Log:
  Add detection logic for the U160 family of adaptec controllers.  These
  controllers will run at U2 speeds until I can complete the U160 support
  for this driver.
  
  Correct a termination buglet for the 2940UW-Pro.
  
  Be more paranoid in how we probe and enable external ram, fast external
  ram timing and external ram parity checking.  We should now work on
  20ns and 8bit SRAM parts.
  
  Perform initial setup for the DT feature on cards that support it.
  
  Factorize and clean up code.  Use tables where it makes sense, etc.
  
  Add some delays in dealing with the board control logic.  I've never
  seen this code fail, but with the ever increasing speed of processors,
  its better to insert deterministic delays just to be safe.  This stuff
  is only touched during probe and attach, so the extra delay is of no
  concern.
  
  Revision  Changes    Path
  1.24      +314 -148  src/sys/pci/ahc_pci.c


  Modified files:
    sys/dev/aic7xxx      93cx6.c aic7xxx.c aic7xxx.h aic7xxx.reg 
                         aic7xxx.seq 
  Log:
  Update copyrights to Y2K.
  
  93cx6.c:
  	Make the SRAM dump output a little prettier.
  
  aic7xxx.c:
  	Store all SG entries into our SG array in kernel space.
  	This makes data-overrun and other error reporting more
  	useful as we can dump all SG entries.  In the past,
  	we only stored the SG entries that the sequencer might
  	need to access, which meant we skipped the first element
  	that is embedded into the SCB.
  
  	Add a table of chip strings and replace ugly switch
  	statements with table lookups.
  
  	Add a table with bus phase strings and message reponses
  	to parity errors in those phases.  Use the table to
  	pretty print bus phase messages as well as collapse
  	another switch statement.
  
  	Fix a bug in target mode that could cause us to unpause
  	the sequencer early in bus reset processing.
  
  	Add the 80MHz/DT mode into our syncrate table.  This
  	rate is not yet used or enabled.
  
  	Correct some comments, clean up some code...
  
  aic7xxx.h:
  	Add U160 controller feature information.
  
  	Add some more bit fields for various SEEPROM formats.
  
  aic7xxx.reg:
  	Add U160 register and register bit definitions.
  
  aic7xxx.seq:
  	Make phasemis state tracking more straight forward.  This
  	avoids the consumption of SINDEX which is a very useful register.
  
  	For the U160 chips, you must use the 'mov' instruction to
  	update DFCNTRL.  Using 'or' to set the PRELOADED bit is
  	completely ineffective.
  
  	At the end of the command phase, wair for our ACK signal
  	to de-assert before disabling the SCSI dma engine.  For
  	slow devices, this avoids clearing the ACK before the
  	other end has had a chance to see it and lower REQ.
  
  Revision  Changes    Path
  1.5       +3 -3      src/sys/dev/aic7xxx/93cx6.c
  1.40      +198 -153  src/sys/dev/aic7xxx/aic7xxx.c
  1.15      +37 -20    src/sys/dev/aic7xxx/aic7xxx.h
  1.19      +61 -3     src/sys/dev/aic7xxx/aic7xxx.reg
  1.93      +16 -14    src/sys/dev/aic7xxx/aic7xxx.seq



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