From owner-freebsd-hackers@FreeBSD.ORG Mon Sep 19 12:41:19 2011 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 47F5E106566C; Mon, 19 Sep 2011 12:41:19 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from cyrus.watson.org (cyrus.watson.org [65.122.17.42]) by mx1.freebsd.org (Postfix) with ESMTP id 1D35B8FC0C; Mon, 19 Sep 2011 12:41:19 +0000 (UTC) Received: from bigwig.baldwin.cx (66.111.2.69.static.nyinternet.net [66.111.2.69]) by cyrus.watson.org (Postfix) with ESMTPSA id AEE5746B45; Mon, 19 Sep 2011 08:41:18 -0400 (EDT) Received: from jhbbsd.localnet (unknown [209.249.190.124]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id 5023D8A02E; Mon, 19 Sep 2011 08:41:18 -0400 (EDT) From: John Baldwin To: freebsd-hackers@freebsd.org Date: Mon, 19 Sep 2011 08:23:32 -0400 User-Agent: KMail/1.13.5 (FreeBSD/8.2-CBSD-20110617; KDE/4.5.5; amd64; ; ) References: <4E744BCE.7060302@sepehrs.com> <20110919020131.GA11657@onelab2.iet.unipi.it> In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201109190823.32871.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.6 (bigwig.baldwin.cx); Mon, 19 Sep 2011 08:41:18 -0400 (EDT) Cc: jfv@freebsd.org, pyunyh@gmail.com, Hooman Fazaeli , Luigi Rizzo , Arnaud Lacombe Subject: Re: intel checksum offload X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Sep 2011 12:41:19 -0000 On Sunday, September 18, 2011 10:48:32 pm Arnaud Lacombe wrote: > As the PCI spec is not public, I've not been able to find out from the > few public datasheet how the PCI MSI-X capability field is first > programmed. I'd assume that the BIOS is using the data in the NVM to > program it at power up. "PCI System Architecture" is quite public at Amazon. It's not the spec, but it will certainly give you enough info to understand MSI and it covers the question you are asking well enough. The MSI config registers are not touched by the BIOS at all (at least not in a standard way). It is the responsibility of the device to setup the read-only fields in the MSI and MSI-X config registers on reset. -- John Baldwin