From owner-freebsd-mips@FreeBSD.ORG Thu Feb 20 05:05:57 2014 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 59C0BC85; Thu, 20 Feb 2014 05:05:57 +0000 (UTC) Received: from mail-lb0-x22a.google.com (mail-lb0-x22a.google.com [IPv6:2a00:1450:4010:c04::22a]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 791AC112A; Thu, 20 Feb 2014 05:05:56 +0000 (UTC) Received: by mail-lb0-f170.google.com with SMTP id u14so984089lbd.15 for ; Wed, 19 Feb 2014 21:05:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=UZp38coPL610p4LsTBtJSWC7HCpIpWE11LZ6ghC6lHE=; b=qkgxzMfy4cJwYYQ9etGh6yjx+H95nwM9cDBo9zqD3cGi+iW53HmtAnMLoCBGES0Mdo vMs1gqd1QxufUIsdEqALUtXTrp8UbozegpNj8b66VoxrQ0G9oXBUNKaHDIt6B+gBSufO 53DaOUXKGqXqjLnTxC+WBfjKFLaRBHsfexltLIWvlDEatRIjxNutK4/xvypAXsrM+E01 Uav1JYkP8eSYFylk3zvcKZtN1LjNUqQnD1Meqc111K3nIIy+IiuOO9kUrOniZrKSGmOX nDHwHLDSjqao8JDGD6kq3dIfg5ZqupQ8Tt5l1cVK8nOXLBfCTylpDkalucD/nG4zctmg gjYw== MIME-Version: 1.0 X-Received: by 10.112.134.38 with SMTP id ph6mr26956819lbb.16.1392872754495; Wed, 19 Feb 2014 21:05:54 -0800 (PST) Received: by 10.112.189.8 with HTTP; Wed, 19 Feb 2014 21:05:54 -0800 (PST) In-Reply-To: References: Date: Thu, 20 Feb 2014 10:35:54 +0530 Message-ID: Subject: Re: [RFC] 16K page size for kernel thread stack (patch) From: "Jayachandran C." To: Juli Mallett Content-Type: text/plain; charset=ISO-8859-1 Cc: "freebsd-mips@freebsd.org" X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Feb 2014 05:05:57 -0000 On Thu, Feb 20, 2014 at 1:19 AM, Juli Mallett wrote: > On Wed, Feb 19, 2014 at 11:41 AM, Stacey Son wrote: >> >> On Feb 18, 2014, at 7:58 PM, Adrian Chadd wrote: >> > I don't think the mips24k/mips74k cores I have support ULRI. >> >> I am starting to wonder which mips CPUs actually do have an ULRI. >> > > Basically-none. Some sources I've read from when the rdhwr approach was > first implemented clearly thought it would pretty much never be implemented > in hardware, and certainly most implementations after it became widespread > didn't implement it, and its use only became common in the recent past. > Until we started using it for TLS, GXemul would exit rather than trap on > the rdhwr. I don't believe I've ever possessed a piece of hardware which > actually implements the register itself, and there's actually a huge > disincentive to do so because a lot of software has been written now which > assumes that rdhwr will always trap and be implemented in software, and so > won't set up the actual hardware register with the right value, breaking > existing software. The Broadcom XLP also has rdhwr (with register 29 implemented). The current emulation we have of rdhwr can be improved quite a bit, I think we should have a handler for reserved exception in the mips exception table and fix up rdhwr without doing full kernel entry/exit. Currently it is routed thru General Exception and trap() JC.