From owner-svn-src-head@freebsd.org Fri Jan 27 04:08:25 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id AA7AACC3CB6; Fri, 27 Jan 2017 04:08:25 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 5D6C11A43; Fri, 27 Jan 2017 04:08:25 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v0R48O7C076346; Fri, 27 Jan 2017 04:08:24 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v0R48OcL076344; Fri, 27 Jan 2017 04:08:24 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201701270408.v0R48OcL076344@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Fri, 27 Jan 2017 04:08:24 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r312859 - head/sys/arm/ti/am335x X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2017 04:08:25 -0000 Author: ian Date: Fri Jan 27 04:08:24 2017 New Revision: 312859 URL: https://svnweb.freebsd.org/changeset/base/312859 Log: Configure the timer capture pin to input mode in the timer control register, in addition to configuring it as input with the pinmux driver. There was a control register bit commented as "no desc in datasheet". A later revision of the manual reveals the bit to be an input/output control for the timer pin. In addition to configuring capture or pulse mode, you apparently have to separately configure the pin direction in the timer control register. Before this change, the timer block was apparently driving a signal onto a pad configured by pinmux as input. Capture mode still accidentally worked for me during testing because I was using a very strong signal source that just out-muscled the weaker drive from the misconfigured pin. Modified: head/sys/arm/ti/am335x/am335x_dmtpps.c head/sys/arm/ti/am335x/am335x_dmtreg.h Modified: head/sys/arm/ti/am335x/am335x_dmtpps.c ============================================================================== --- head/sys/arm/ti/am335x/am335x_dmtpps.c Fri Jan 27 03:44:50 2017 (r312858) +++ head/sys/arm/ti/am335x/am335x_dmtpps.c Fri Jan 27 04:08:24 2017 (r312859) @@ -463,6 +463,14 @@ dmtpps_attach(device_t dev) sc->tmr_num = ti_hwmods_get_unit(dev, "timer"); snprintf(sc->tmr_name, sizeof(sc->tmr_name), "DMTimer%d", sc->tmr_num); + /* + * Configure the timer pulse/capture pin to input/capture mode. This is + * required in addition to configuring the pin as input with the pinmux + * controller (which was done via fdt data or tunable at probe time). + */ + sc->tclr = DMT_TCLR_GPO_CFG; + DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr); + /* Set up timecounter hardware, start it. */ DMTIMER_WRITE4(sc, DMT_TSICR, DMT_TSICR_RESET); while (DMTIMER_READ4(sc, DMT_TIOCP_CFG) & DMT_TIOCP_RESET) Modified: head/sys/arm/ti/am335x/am335x_dmtreg.h ============================================================================== --- head/sys/arm/ti/am335x/am335x_dmtreg.h Fri Jan 27 03:44:50 2017 (r312858) +++ head/sys/arm/ti/am335x/am335x_dmtreg.h Fri Jan 27 04:08:24 2017 (r312859) @@ -62,7 +62,7 @@ #define DMT_TCLR_TRGMODE_BOTH (2 << 10) /* Trigger on match + ovflow */ #define DMT_TCLR_PWM_PTOGGLE (1 << 12) /* PWM toggles */ #define DMT_TCLR_CAP_MODE_2ND (1 << 13) /* Capture second event mode */ -#define DMT_TCLR_GPO_CFG (1 << 14) /* (no descr in datasheet) */ +#define DMT_TCLR_GPO_CFG (1 << 14) /* Tmr pin conf, 0=out, 1=in */ #define DMT_TCRR 0x3C /* Counter Register */ #define DMT_TLDR 0x40 /* Load Reg */ #define DMT_TTGR 0x44 /* Trigger Reg */