Skip site navigation (1)Skip section navigation (2)
Date:      Fri, 11 Jan 2002 23:24:40 -0800
From:      Peter Wemm <peter@wemm.org>
To:        Bruce Evans <bde@zeta.org.au>
Cc:        Mark Murray <mark@grondar.za>, Chris Faulhaber <jedgar@fxp.org>, scottl@FreeBSD.ORG, smp@FreeBSD.ORG
Subject:   Re: P5 vs. SMP, part 2 
Message-ID:  <20020112072440.3273038FD@overcee.netplex.com.au>
In-Reply-To: <20020112173153.G4872-100000@gamplex.bde.org> 

next in thread | previous in thread | raw e-mail | index | archive | help
Bruce Evans wrote:
> On Fri, 11 Jan 2002, Peter Wemm wrote:
> 
> > The problem is that the AP cpus were running with the CR0_CD (cache disable
    )
> > and CR0_NW (cache writethrough, not writeback).  This is very bad. :-]
> >
> > PPro and above bioses seem to cause the AP cpus enter the kernel with cache
> > enabled, so that this looks like it should be a p5/i586 problem only.
> 
> Where were they set before?

They used to be done as a side effect of a load_cr0(magic_number);
and several other bits were tweaked later.  That's what broke, no baseline
was set.

cvs diff -u -r1.119 -r1.120 -kk mp_machdep.c
+++ mp_machdep.c        11 Aug 2000 09:05:11 -0000      1.120
@@ -487,8 +487,6 @@
        common_tssd = *tss_gdt;
        ltr(gsel_tss);
 
-       load_cr0(0x8005003b);           /* XXX! */
-
        pmap_set_opt();
 }
 
@@ -623,13 +621,6 @@
 
        /* start each Application Processor */
        start_all_aps(boot_addr);
-
-       /* 
-        * The init process might be started on a different CPU now,
-        * and the boot CPU might not call prepare_usermode to get
-        * cr0 correctly configured. Thus we initialize cr0 here.
-        */
-       load_cr0(rcr0() | CR0_WP | CR0_AM);
 }
 
 
@@ -2375,8 +2366,8 @@
 
        printf("SMP: AP CPU #%d Launched!\n", cpuid);
 
-       /* XXX FIXME: i386 specific, and redundant: Setup the FPU. */
-       load_cr0((rcr0() & ~CR0_EM) | CR0_MP | CR0_NE | CR0_TS);
+       /* set up CPU registers and state */
+       cpu_setregs();
 
        /* set up FPU state on the AP */
        npxinit(__INITIAL_NPXCW__);


> initcpu() has a mazing amount of code for setting these bits.

Yes.  And it sets some machine dependent registers on the BSP only that
is missing on the AP's I think.

> We should set all CR* bits that we know and care about.  We also sort of
> depend on BIOSes to clear CR4_TSD so that the TSC works in user mode.
> The TSC in user mode is not really supported, but I often use it.

Yes, depending on bios leftovers has proven itself to be a problem.  It is
just lucky that the P6+ bioses tend to duplicate the BSP 'cache enable'
bios setting on the AP's when waking them up and doing the warm start
vector for mpboot.s.

Cheers,
-Peter
--
Peter Wemm - peter@FreeBSD.org; peter@yahoo-inc.com; peter@netplex.com.au
"All of this is for nothing if we don't go to the stars" - JMS/B5


To Unsubscribe: send mail to majordomo@FreeBSD.org
with "unsubscribe freebsd-smp" in the body of the message




Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?20020112072440.3273038FD>