From owner-freebsd-hackers Thu Apr 6 11:49:53 1995 Return-Path: hackers-owner Received: (from majordom@localhost) by freefall.cdrom.com (8.6.10/8.6.6) id LAA04475 for hackers-outgoing; Thu, 6 Apr 1995 11:49:53 -0700 Received: from dkuug.dk (dkuug.dk [193.88.44.89]) by freefall.cdrom.com (8.6.10/8.6.6) with SMTP id LAA04468 for ; Thu, 6 Apr 1995 11:49:43 -0700 Received: from kmd-ac.dk by dkuug.dk with UUCP id AA09676 (5.65c8/IDA-1.4.4j for freebsd.org!hackers); Thu, 6 Apr 1995 20:49:37 +0200 Message-Id: <199504061849.AA09676@dkuug.dk> Subject: Intel 486"Enhanced Write Back" question To: hackers@FreeBSD.org (FreeBSD hackers) Date: Thu, 6 Apr 1995 20:47:17 +0000 (GMT) From: "Soeren Schmidt" X-Mailer: ELM [version 2.4 PL22] Content-Type: text Content-Length: 481 X-Charset: ASCII X-Char-Esc: 29 Sender: hackers-owner@FreeBSD.org Precedence: bulk I have these new 486 "enhanced writeback" CPU's lying around, but I cannot use the WB feature. I've read that the CPU determines if it shall work as a WB or WT chip by reading the level on some pin on reset. This makes sense as old motherboard designs wouldn't support this feature then. Now the question is which pin ?? -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Soren Schmidt (sos@FreeBSD.org | sos@kmd-ac.dk) FreeBSD Core Team ..