Date: Sat, 29 May 2010 17:17:08 GMT From: Volodymyr Serbinenko <phcoder@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 178958 for review Message-ID: <201005291717.o4THH8ND078772@repoman.freebsd.org>
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http://p4web.freebsd.org/@@178958?ac=10 Change 178958 by phcoder@phcoder_ on 2010/05/29 17:16:53 Fix p4 copy and resync with bzr one. Now I drop into debugger and receive a sensible trace. Affected files ... .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/conf/ldscript.mips#2 edit .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/conf/ldscript.mips.mips64#2 edit .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/conf/YEELOONG#1 add .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/include/cpu.h#2 edit .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/include/cpufunc.h#2 edit .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/include/cpuregs.h#2 edit .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/cpu.c#2 edit .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/db_trace.c#2 edit .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/exception.S#2 edit .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/locore.S#2 edit .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/multiboot2.h#1 add .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/yeeloong/clock.c#1 add .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/yeeloong/files.yeeloong#1 add .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/yeeloong/std.yeeloong#1 add .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/yeeloong/uart_bus_yeeloongusart.c#1 add .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/yeeloong/uart_cpu_yeeloongusart.c#1 add .. //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/yeeloong/yeeloong_machdep.c#1 add Differences ... ==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/conf/ldscript.mips#2 (text+ko) ==== @@ -64,6 +64,7 @@ .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) } .rodata1 : { *(.rodata1) } .interp : { *(.interp) } + .multiboot : { *(.multiboot) } .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } ==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/conf/ldscript.mips.mips64#2 (text+ko) ==== @@ -45,6 +45,7 @@ /* Read-only sections, merged into text segment: */ . = KERNLOADADDR + SIZEOF_HEADERS; .interp : { *(.interp) } + .multiboot : { *(.multiboot) } .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } ==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/include/cpu.h#2 (text+ko) ==== @@ -162,11 +162,17 @@ /* * Location of exception vectors. */ -#define RESET_EXC_VEC 0xbfc00000 -#define TLB_MISS_EXC_VEC 0x80000000 -#define XTLB_MISS_EXC_VEC 0x80000080 -#define CACHE_ERR_EXC_VEC 0x80000100 -#define GEN_EXC_VEC 0x80000180 +#ifdef __mips_n64 +#define MIPS_VADDR(x) (0xffffffff00000000 | (x)) +#else +#define MIPS_VADDR(x) (x) +#endif + +#define RESET_EXC_VEC MIPS_VADDR(0xbfc00000) +#define TLB_MISS_EXC_VEC MIPS_VADDR(0x80000000) +#define XTLB_MISS_EXC_VEC MIPS_VADDR(0x80000080) +#define CACHE_ERR_EXC_VEC MIPS_VADDR(0x80000100) +#define GEN_EXC_VEC MIPS_VADDR(0x80000180) /* * Coprocessor 0 registers: ==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/include/cpufunc.h#2 (text+ko) ==== @@ -142,6 +142,10 @@ #undef MIPS_RDRW64_COP0 #endif +#if __mips == 32 || __mips == 64 +#define MIPS_HAS_CP0_SELECTORS 1 +#endif + #define MIPS_RDRW32_COP0(n,r) \ static __inline uint32_t \ mips_rd_ ## n (void) \ @@ -164,6 +168,8 @@ mips_barrier(); \ } struct __hack +#ifdef MIPS_HAS_CP0_SELECTORS + #define MIPS_RDRW32_COP0_SEL(n,r,s) \ static __inline uint32_t \ mips_rd_ ## n(void) \ @@ -186,6 +192,9 @@ mips_barrier(); \ } struct __hack +#endif + + #ifdef TARGET_OCTEON static __inline void mips_sync_icache (void) { @@ -201,9 +210,11 @@ MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE); MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG); +#ifdef MIPS_HAS_CP0_SELECTORS MIPS_RDRW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1); MIPS_RDRW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2); MIPS_RDRW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3); +#endif MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT); MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX); MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED); @@ -219,12 +230,17 @@ #endif MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID); /* XXX 64-bit? */ +#ifdef MIPS_HAS_CP0_SELECTORS MIPS_RDRW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); +#endif MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); +#ifdef MIPS_HAS_CP0_SELECTORS MIPS_RDRW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1); MIPS_RDRW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2); MIPS_RDRW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3); +#endif MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); +#ifdef MIPS_HAS_CP0_SELECTORS MIPS_RDRW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1); MIPS_RDRW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2); MIPS_RDRW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3); @@ -233,6 +249,7 @@ MIPS_RDRW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1); MIPS_RDRW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2); MIPS_RDRW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3); +#endif #undef MIPS_RDRW32_COP0 ==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/include/cpuregs.h#2 (text+ko) ==== @@ -109,8 +109,14 @@ #define MIPS_XKSEG_START 0xc000000000000000 #define MIPS_XKSEG_END 0xc00000ff80000000 +#if __mips == 32 || __mips == 64 +#define SSNOP ssnop +#else +#define SSNOP nop +#endif + /* CPU dependent mtc0 hazard hook */ -#ifdef TARGET_OCTEON +#if defined (TARGET_OCTEON) || defined (TARGET_YEELOONG) #define COP0_SYNC nop; nop; nop; nop; nop; #elif defined(CPU_SB1) #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop ==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/cpu.c#2 (text+ko) ==== @@ -69,8 +69,6 @@ { u_int32_t prid; u_int32_t cfg0; - u_int32_t cfg1; - u_int32_t tmp; memset(cpuinfo, 0, sizeof(struct mips_cpuinfo)); @@ -87,46 +85,61 @@ ((cfg0 & MIPS_CONFIG0_MT_MASK) >> MIPS_CONFIG0_MT_SHIFT); cpuinfo->icache_virtual = cfg0 & MIPS_CONFIG0_VI; - /* If config register selection 1 does not exist, exit. */ - if (!(cfg0 & MIPS3_CONFIG_CM)) - return; + +#ifdef MIPS_HAS_CP0_SELECTORS + { + /* Learn TLB size and L1 cache geometry. */ + u_int32_t cfg1 = mips_rd_config1(); + u_int32_t tmp; + + /* If config register selection 1 does not exist, exit. */ + if (!(cfg0 & MIPS3_CONFIG_CM)) + panic ("unable to retrieve cache parameters"); + + cpuinfo->tlb_nentries = + ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; - /* Learn TLB size and L1 cache geometry. */ - cfg1 = mips_rd_config1(); - cpuinfo->tlb_nentries = - ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; + /* L1 instruction cache. */ + tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT; + if (tmp != 0) { + cpuinfo->l1.ic_linesize = 1 << (tmp + 1); + cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1; + cpuinfo->l1.ic_nsets = + 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); + cpuinfo->l1.ic_size = + cpuinfo->l1.ic_linesize * cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_nways; + } - /* L1 instruction cache. */ - tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT; - if (tmp != 0) { - cpuinfo->l1.ic_linesize = 1 << (tmp + 1); - cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1; - cpuinfo->l1.ic_nsets = - 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); - cpuinfo->l1.ic_size = - cpuinfo->l1.ic_linesize * cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_nways; + /* L1 data cache. */ + tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT; + if (tmp != 0) { + cpuinfo->l1.dc_linesize = 1 << (tmp + 1); + cpuinfo->l1.dc_nways = + (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1; + cpuinfo->l1.dc_nsets = + 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6); + } +#ifdef TARGET_OCTEON + /* + * Octeon does 128 byte line-size. But Config-Sel1 doesn't show + * 128 line-size, 1 Set, 64 ways. + */ + cpuinfo->l1.dc_linesize = 128; + cpuinfo->l1.dc_nsets = 1; + cpuinfo->l1.dc_nways = 64; +#endif + cpuinfo->l1.dc_size = cpuinfo->l1.dc_linesize + * cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_nways; } - - /* L1 data cache. */ - tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT; - if (tmp != 0) { - cpuinfo->l1.dc_linesize = 1 << (tmp + 1); - cpuinfo->l1.dc_nways = - (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1; - cpuinfo->l1.dc_nsets = - 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6); +#elif defined (TARGET_YEELOONG) + { + cpuinfo->tlb_nentries = 64; + cpuinfo->l1.ic_linesize = 32; + cpuinfo->l1.dc_linesize = 32; } -#ifdef TARGET_OCTEON - /* - * Octeon does 128 byte line-size. But Config-Sel1 doesn't show - * 128 line-size, 1 Set, 64 ways. - */ - cpuinfo->l1.dc_linesize = 128; - cpuinfo->l1.dc_nsets = 1; - cpuinfo->l1.dc_nways = 64; +#else +#error unknown architecture without selector support #endif - cpuinfo->l1.dc_size = cpuinfo->l1.dc_linesize - * cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_nways; } void @@ -150,7 +163,7 @@ void cpu_identify(void) { - uint32_t cfg0, cfg1, cfg2, cfg3; + uint32_t cfg0; printf("cpu%d: ", 0); /* XXX per-cpu */ switch (cpuinfo.cpu_vendor) { case MIPS_PRID_CID_MTI: @@ -236,27 +249,33 @@ if (!(cfg0 & MIPS3_CONFIG_CM)) return; - cfg1 = mips_rd_config1(); - printf(" Config1=0x%b\n", cfg1, - "\20\7COP2\6MDMX\5PerfCount\4WatchRegs\3MIPS16\2EJTAG\1FPU"); +#ifdef MIPS_HAS_CP0_SELECTORS + { + uint32_t cfg1, cfg2, cfg3; + + cfg1 = mips_rd_config1(); + printf(" Config1=0x%b\n", cfg1, + "\20\7COP2\6MDMX\5PerfCount\4WatchRegs\3MIPS16\2EJTAG\1FPU"); - /* If config register selection 2 does not exist, exit. */ - if (!(cfg1 & MIPS3_CONFIG_CM)) - return; - cfg2 = mips_rd_config2(); - /* - * Config2 contains no useful information other then Config3 - * existence flag - */ + /* If config register selection 2 does not exist, exit. */ + if (!(cfg1 & MIPS3_CONFIG_CM)) + return; + cfg2 = mips_rd_config2(); + /* + * Config2 contains no useful information other then Config3 + * existence flag + */ - /* If config register selection 3 does not exist, exit. */ - if (!(cfg2 & MIPS3_CONFIG_CM)) - return; - cfg3 = mips_rd_config3(); + /* If config register selection 3 does not exist, exit. */ + if (!(cfg2 & MIPS3_CONFIG_CM)) + return; + cfg3 = mips_rd_config3(); /* Print Config3 if it contains any useful info */ - if (cfg3 & ~(0x80000000)) - printf(" Config3=0x%b\n", cfg3, "\20\2SmartMIPS\1TraceLogic"); + if (cfg3 & ~(0x80000000)) + printf(" Config3=0x%b\n", cfg3, "\20\2SmartMIPS\1TraceLogic"); + } +#endif } static struct rman cpu_hardirq_rman; ==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/db_trace.c#2 (text+ko) ==== @@ -49,9 +49,19 @@ #define MIPS_END_OF_FUNCTION(ins) ((ins) == 0x03e00008) /* - * kdbpeekD(addr) - skip one word starting at 'addr', then read the second word + * kdbpeekD(addr) - read double word. */ -#define kdbpeekD(addr) kdbpeek(((int *)(addr)) + 1) + +static inline register_t +kdbpeekD (uintptr_t addr) { +#ifdef __MIPSEL__ + return ((register_t) kdbpeek ((int *) addr)) + | (((register_t) kdbpeek ((int *) addr + 1)) << 32); +#else + return ((register_t) kdbpeek ((int *) addr + 1)) + | (((register_t) kdbpeek ((int *) addr)) << 32); +#endif +} /* * Functions ``special'' enough to print by name @@ -119,6 +129,8 @@ unsigned instr, mask; unsigned int frames = 0; int more, stksize, j; + const uintptr_t kseg0_start = sizeof (uintptr_t) + ? 0xffffffff80000000ULL : 0x80000000; /* Jump here when done with a frame, to start a new one */ loop: @@ -140,7 +152,7 @@ } /* check for bad SP: could foul up next frame */ /*XXX MIPS64 bad: this hard-coded SP is lame */ - if (sp & 3 || sp < 0x80000000) { + if (sp & 3 || (uintptr_t) sp < kseg0_start) { (*printfn) ("SP 0x%x: not in kernel\n", sp); ra = 0; subr = 0; @@ -181,7 +193,7 @@ } /* check for bad PC */ /*XXX MIPS64 bad: These hard coded constants are lame */ - if (pc & 3 || pc < (uintptr_t)0x80000000) { + if (pc & 3 || (uintptr_t)pc < kseg0_start) { (*printfn) ("PC 0x%x: not in kernel\n", pc); ra = 0; goto done; @@ -303,32 +315,34 @@ mask |= (1 << i.IType.rt); switch (i.IType.rt) { case 4:/* a0 */ - args[0] = kdbpeekD((int *)(sp + (short)i.IType.imm)); + args[0] = kdbpeekD(sp + (short)i.IType.imm); valid_args[0] = 1; break; case 5:/* a1 */ - args[1] = kdbpeekD((int *)(sp + (short)i.IType.imm)); + args[1] = kdbpeekD(sp + (short)i.IType.imm); valid_args[1] = 1; break; case 6:/* a2 */ - args[2] = kdbpeekD((int *)(sp + (short)i.IType.imm)); + args[2] = kdbpeekD(sp + (short)i.IType.imm); valid_args[2] = 1; break; case 7:/* a3 */ - args[3] = kdbpeekD((int *)(sp + (short)i.IType.imm)); + args[3] = kdbpeekD(sp + (short)i.IType.imm); valid_args[3] = 1; break; case 31: /* ra */ - ra = kdbpeekD((int *)(sp + (short)i.IType.imm)); + ra = kdbpeekD(sp + (short)i.IType.imm); } break; case OP_ADDI: case OP_ADDIU: + case OP_DADDIU: + case OP_DADDI: /* look for stack pointer adjustment */ if (i.IType.rs != 29 || i.IType.rt != 29) break; @@ -337,17 +351,18 @@ } done: - (*printfn) ("%s+%x (", fn_name(subr), pc - subr); + (*printfn) ("%s+%lx (", fn_name(subr), (unsigned long) (pc - subr)); for (j = 0; j < 4; j ++) { if (j > 0) (*printfn)(","); if (valid_args[j]) - (*printfn)("%x", args[j]); + (*printfn)("%lx", (unsigned long) args[j]); else (*printfn)("?"); } - (*printfn) (") ra %x sp %x sz %d\n", ra, sp, stksize); + (*printfn) (") ra %lx sp %lx sz %ld\n", (unsigned long) ra, + (unsigned long) sp, (long) stksize); if (ra) { if (pc == ra && stksize == 0) ==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/exception.S#2 (text+ko) ==== @@ -854,12 +854,12 @@ nop tlbwi eret - ssnop + SSNOP tlb_insert_random: tlbwr eret - ssnop + SSNOP 3: /* ==== //depot/projects/soc2010/phcoder_yeeloong/src/sys/mips/mips/locore.S#2 (text+ko) ==== @@ -69,9 +69,38 @@ #include <machine/cpu.h> #include <machine/cpuregs.h> #include <machine/regnum.h> +#define ASM_FILE +#include "multiboot2.h" #include "assym.s" + .section ".multiboot", "a" + + /* Align 64 bits boundary. */ + .align 8 + + /* Multiboot header. */ +multiboot_header: + /* magic */ + .long MULTIBOOT2_HEADER_MAGIC + .long MULTIBOOT_ARCHITECTURE_MIPS32 + /* Header length. */ + .long multiboot_header_end - multiboot_header + /* checksum */ + .long -(MULTIBOOT2_HEADER_MAGIC + MULTIBOOT_ARCHITECTURE_MIPS32 + (multiboot_header_end - multiboot_header)) +framebuffer_tag_start: + .short MULTIBOOT_HEADER_TAG_FRAMEBUFFER + .short MULTIBOOT_HEADER_TAG_OPTIONAL + .long framebuffer_tag_end - framebuffer_tag_start + .long 1024 + .long 600 + .long 16 +framebuffer_tag_end: + .short MULTIBOOT_HEADER_TAG_END + .short 0 + .long 8 +multiboot_header_end: + .data #ifdef YAMON GLOBAL(fenvp) @@ -130,13 +159,15 @@ COP0_SYNC /* Make sure KSEG0 is cached */ - li t0, CFG_K0_CACHED + mfc0 t0, MIPS_COP_0_CONFIG + ori t0, CFG_K0_CACHED mtc0 t0, MIPS_COP_0_CONFIG COP0_SYNC /* Read and store the PrID FPU ID for CPU identification, if any. */ mfc0 t2, COP_0_STATUS_REG mfc0 t0, MIPS_COP_0_PRID + #ifdef CPU_HAVEFPU and t2, MIPS_SR_COP_1_BIT beqz t2, 1f
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