From owner-p4-projects@FreeBSD.ORG Tue Jan 29 08:24:48 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 3303516A420; Tue, 29 Jan 2008 08:24:48 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id D45C216A417 for ; Tue, 29 Jan 2008 08:24:47 +0000 (UTC) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id C2B1A13C45D for ; Tue, 29 Jan 2008 08:24:47 +0000 (UTC) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m0T8Ol6j010880 for ; Tue, 29 Jan 2008 08:24:47 GMT (envelope-from imp@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m0T8Olcn010877 for perforce@freebsd.org; Tue, 29 Jan 2008 08:24:47 GMT (envelope-from imp@freebsd.org) Date: Tue, 29 Jan 2008 08:24:47 GMT Message-Id: <200801290824.m0T8Olcn010877@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to imp@freebsd.org using -f From: Warner Losh To: Perforce Change Reviews Cc: Subject: PERFORCE change 134362 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Jan 2008 08:24:48 -0000 http://perforce.freebsd.org/chv.cgi?CH=134362 Change 134362 by imp@imp_lighthouse on 2008/01/29 08:24:07 Merge some changes from the cavium tree, lots of work needed here, so you should expect it not to work just yet. o Provide a simple secondary start routine for all cores that come up when we're not doing SMP (I'd think it would be better to pause the core, but I didn't see a way to do that). o Restore stack code. TD_PCB was assumed to be 8 byte aligned, but it seems to only be 4 byte aligned. Cope by clearing bits to make it 8-byte aligned. o On the octeon, save the app descriptor address. The octeon code wants to parse this. This is in the same class as the YAMON and CFE saving, but is it really needed? I don't know. o don't li 0 when moving from zero works better. o Put KSEG0 into cached mode. I don't know why the cavium code does this, but maybe it is to put it into uncached mode easily. o Remove redundant setting of STATUS reg. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#18 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/locore.S#18 (text+ko) ==== @@ -83,6 +83,10 @@ GLOBAL(cfe_vector) .space 4 #endif +#ifdef CPU_OCTEON +GLOBAL(app_descriptor_addr) + .space 8 +#endif GLOBAL(stackspace) .space NBPG /* Smaller than it should be since it's temp. */ .align 8 @@ -96,10 +100,6 @@ VECTOR(_locore, unknown) /* UNSAFE TO USE a0..a3, since some bootloaders pass that to us */ - # Keep firmware exception handlers until the kernel sets up its own - # exception handlers. - li v0, SR_BOOT_EXC_VEC - mtc0 v0, COP_0_STATUS_REG # Disable interrupts. mtc0 zero, COP_0_CAUSE_REG # Clear soft interrupts /* @@ -125,15 +125,19 @@ or t2, t1 mtc0 t2, COP_0_STATUS_REG COP0_SYNC - /* Extra nops for the FPU to spin up. */ + + /* Make sure KSEG0 is cached */ + li t0, CFG_K0_CACHED + mtc0 t0, MIPS_COP_0_CONFIG + COP0_SYNC + + /* Read and store the PrID FPU ID for CPU identification, if any. */ mfc0 t2, COP_0_STATUS_REG - - /* Read and store the PrID FPU ID for CPU identification. */ mfc0 t0, MIPS_COP_0_PRID #ifndef CPU_NOFPU and t2, MIPS_SR_COP_1_BIT beqz t2, 1f - li t1, 0x0 + move t1, zero cfc1 t1, MIPS_FPU_ID 1: #else @@ -141,7 +145,7 @@ * This platform has no FPU, and attempting to detect one * using the official method causes an exception. */ - li t1, 0x0 + move t1, zero #endif sw t0, _C_LABEL(cpu_id) sw t1, _C_LABEL(fpu_id) @@ -171,6 +175,10 @@ sw a2, _C_LABEL(cfe_vector)/* Firmware entry vector */ no_cfe: #endif +#ifdef CPU_OCTEON + la a0, app_descriptor_addr + sw a3, 0(a0) /* Store app descriptor ptr */ +#endif /* * The following needs to be done differently for each platform and @@ -198,6 +206,18 @@ mtcr t1, t2 #endif +#ifdef CPU_OCTEON /* Maybe this is mips32/64 generic? */ + .set push + .set mips32r2 + rdhwr t0, $0 + .set pop +#else + move t0, zero +#endif + /* Stage the secondary cpu start until later */ + bne t0, zero, start_secondary + nop + #ifdef SMP la t0, _C_LABEL(__pcpu) SET_CPU_PCPU(t0) @@ -211,6 +231,12 @@ jal _C_LABEL(platform_start) sw zero, START_FRAME - 8(sp) # Zero out old fp for debugger + la sp, _C_LABEL(thread0) + lw a0, TD_PCB(sp) + li t0, ~7 + and a0, a0, t0 + subu sp, a0, START_FRAME + jal _C_LABEL(mi_startup) # mi_startup(frame) sw zero, START_FRAME - 8(sp) # Zero out old fp for debugger @@ -231,6 +257,10 @@ nop jal _C_LABEL(smp_init_secondary) nop +#else +start_secondary: + b start_secondary + nop #endif VECTOR_END(_locore)