From owner-p4-projects@FreeBSD.ORG Tue Jan 22 21:07:24 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id B229016A421; Tue, 22 Jan 2008 21:07:24 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 7731D16A419 for ; Tue, 22 Jan 2008 21:07:24 +0000 (UTC) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 6E51E13C4CC for ; Tue, 22 Jan 2008 21:07:24 +0000 (UTC) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m0ML7OIc058484 for ; Tue, 22 Jan 2008 21:07:24 GMT (envelope-from imp@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m0ML7OmE058481 for perforce@freebsd.org; Tue, 22 Jan 2008 21:07:24 GMT (envelope-from imp@freebsd.org) Date: Tue, 22 Jan 2008 21:07:24 GMT Message-Id: <200801222107.m0ML7OmE058481@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to imp@freebsd.org using -f From: Warner Losh To: Perforce Change Reviews Cc: Subject: PERFORCE change 133890 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Jan 2008 21:07:25 -0000 http://perforce.freebsd.org/chv.cgi?CH=133890 Change 133890 by imp@imp_paco-paco on 2008/01/22 21:06:38 First cut at 32-bit version of this. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/tlb32.S#2 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/tlb32.S#2 (text+ko) ==== @@ -94,22 +94,22 @@ ITLBNOPFIX lw a2, 8(a1) lw a3, 12(a1) - dmfc0 t0, COP_0_TLB_HI # Save the current PID. + mfc0 t0, COP_0_TLB_HI # Save the current PID. - dmtc0 a2, COP_0_TLB_LO0 # Set up entry low0. - dmtc0 a3, COP_0_TLB_LO1 # Set up entry low1. + mtc0 a2, COP_0_TLB_LO0 # Set up entry low0. + mtc0 a3, COP_0_TLB_LO1 # Set up entry low1. lw a2, 0(a1) lw a3, 4(a1) mtc0 a0, COP_0_TLB_INDEX # Set the index. - dmtc0 a2, COP_0_TLB_PG_MASK # Set up entry mask. - dmtc0 a3, COP_0_TLB_HI # Set up entry high. + mtc0 a2, COP_0_TLB_PG_MASK # Set up entry mask. + mtc0 a3, COP_0_TLB_HI # Set up entry high. MIPS_CPU_NOP_DELAY tlbwi # Write the TLB MIPS_CPU_NOP_DELAY - dmtc0 t0, COP_0_TLB_HI # Restore the PID. + mtc0 t0, COP_0_TLB_HI # Restore the PID. nop - dmtc0 zero, COP_0_TLB_PG_MASK # Default mask value. + mtc0 zero, COP_0_TLB_PG_MASK # Default mask value. mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX j ra @@ -131,7 +131,7 @@ *-------------------------------------------------------------------------- */ LEAF(Mips_SetPID) - dmtc0 a0, COP_0_TLB_HI # Write the hi reg value + mtc0 a0, COP_0_TLB_HI # Write the hi reg value nop # required for QED5230 nop # required for QED5230 j ra @@ -200,11 +200,11 @@ ITLBNOPFIX mfc0 t1, COP_0_TLB_WIRED li v0, MIPS_KSEG0_START # invalid address - dmfc0 t0, COP_0_TLB_HI # Save the PID + mfc0 t0, COP_0_TLB_HI # Save the PID - dmtc0 v0, COP_0_TLB_HI # Mark entry high as invalid - dmtc0 zero, COP_0_TLB_LO0 # Zero out low entry0. - dmtc0 zero, COP_0_TLB_LO1 # Zero out low entry1. + mtc0 v0, COP_0_TLB_HI # Mark entry high as invalid + mtc0 zero, COP_0_TLB_LO0 # Zero out low entry0. + mtc0 zero, COP_0_TLB_LO1 # Zero out low entry1. mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. /* * Align the starting value (t1) and the upper bound (a0). @@ -218,7 +218,7 @@ bne t1, a0, 1b nop - dmtc0 t0, COP_0_TLB_HI # Restore the PID + mtc0 t0, COP_0_TLB_HI # Restore the PID mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX j ra @@ -246,9 +246,9 @@ ITLBNOPFIX li v0, (PG_HVPN | PG_ASID) and a0, a0, v0 # Make shure valid hi value. - dmfc0 t0, COP_0_TLB_HI # Get current PID + mfc0 t0, COP_0_TLB_HI # Get current PID mfc0 t3, COP_0_TLB_PG_MASK # Save current pgMask - dmtc0 a0, COP_0_TLB_HI # look for addr & PID + mtc0 a0, COP_0_TLB_HI # look for addr & PID MIPS_CPU_NOP_DELAY tlbp # Probe for the entry. MIPS_CPU_NOP_DELAY @@ -256,15 +256,15 @@ li t1, MIPS_KSEG0_START # Load invalid entry. bltz v0, 1f # index < 0 => !found nop - dmtc0 t1, COP_0_TLB_HI # Mark entry high as invalid + mtc0 t1, COP_0_TLB_HI # Mark entry high as invalid - dmtc0 zero, COP_0_TLB_LO0 # Zero out low entry. - dmtc0 zero, COP_0_TLB_LO1 # Zero out low entry. + mtc0 zero, COP_0_TLB_LO0 # Zero out low entry. + mtc0 zero, COP_0_TLB_LO1 # Zero out low entry. MIPS_CPU_NOP_DELAY tlbwi MIPS_CPU_NOP_DELAY 1: - dmtc0 t0, COP_0_TLB_HI # restore PID + mtc0 t0, COP_0_TLB_HI # restore PID mtc0 t3, COP_0_TLB_PG_MASK # Restore pgMask mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX @@ -293,13 +293,13 @@ and t1, a0, 0x1000 # t1 = Even/Odd flag li v0, (PG_HVPN | PG_ASID) and a0, a0, v0 - dmfc0 t0, COP_0_TLB_HI # Save current PID - dmtc0 a0, COP_0_TLB_HI # Init high reg + mfc0 t0, COP_0_TLB_HI # Save current PID + mtc0 a0, COP_0_TLB_HI # Init high reg and a2, a1, PG_G # Copy global bit MIPS_CPU_NOP_DELAY tlbp # Probe for the entry. - dsll a1, a1, 34 - dsrl a1, a1, 34 + sll a1, a1, 2 + srl a1, a1, 2 nop mfc0 v0, COP_0_TLB_INDEX # See what we got bne t1, zero, 2f # Decide even odd @@ -310,16 +310,16 @@ tlbr # update, read entry first MIPS_CPU_NOP_DELAY - dmtc0 a1, COP_0_TLB_LO0 # init low reg0. + mtc0 a1, COP_0_TLB_LO0 # init low reg0. MIPS_CPU_NOP_DELAY tlbwi # update slot found b 4f nop 1: mtc0 zero, COP_0_TLB_PG_MASK # init mask. - dmtc0 a0, COP_0_TLB_HI # init high reg. - dmtc0 a1, COP_0_TLB_LO0 # init low reg0. - dmtc0 a2, COP_0_TLB_LO1 # init low reg1. + mtc0 a0, COP_0_TLB_HI # init high reg. + mtc0 a1, COP_0_TLB_LO0 # init low reg0. + mtc0 a2, COP_0_TLB_LO1 # init low reg1. MIPS_CPU_NOP_DELAY tlbwr # enter into a random slot MIPS_CPU_NOP_DELAY @@ -333,7 +333,7 @@ tlbr # read the entry first MIPS_CPU_NOP_DELAY - dmtc0 a1, COP_0_TLB_LO1 # init low reg1. + mtc0 a1, COP_0_TLB_LO1 # init low reg1. MIPS_CPU_NOP_DELAY tlbwi # update slot found MIPS_CPU_NOP_DELAY @@ -341,15 +341,15 @@ nop 3: mtc0 zero, COP_0_TLB_PG_MASK # init mask. - dmtc0 a0, COP_0_TLB_HI # init high reg. - dmtc0 a2, COP_0_TLB_LO0 # init low reg0. - dmtc0 a1, COP_0_TLB_LO1 # init low reg1. + mtc0 a0, COP_0_TLB_HI # init high reg. + mtc0 a2, COP_0_TLB_LO0 # init low reg0. + mtc0 a1, COP_0_TLB_LO1 # init low reg1. MIPS_CPU_NOP_DELAY tlbwr # enter into a random slot 4: # Make shure pipeline MIPS_CPU_NOP_DELAY - dmtc0 t0, COP_0_TLB_HI # restore PID + mtc0 t0, COP_0_TLB_HI # restore PID mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX j ra @@ -374,17 +374,17 @@ mfc0 v1, COP_0_STATUS_REG # Save the status register. mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX - dmfc0 t0, COP_0_TLB_HI # Get current PID + mfc0 t0, COP_0_TLB_HI # Get current PID mtc0 a0, COP_0_TLB_INDEX # Set the index register MIPS_CPU_NOP_DELAY tlbr # Read from the TLB MIPS_CPU_NOP_DELAY mfc0 t2, COP_0_TLB_PG_MASK # fetch the hi entry - dmfc0 t3, COP_0_TLB_HI # fetch the hi entry - dmfc0 t4, COP_0_TLB_LO0 # See what we got - dmfc0 t5, COP_0_TLB_LO1 # See what we got - dmtc0 t0, COP_0_TLB_HI # restore PID + mfc0 t3, COP_0_TLB_HI # fetch the hi entry + mfc0 t4, COP_0_TLB_LO0 # See what we got + mfc0 t5, COP_0_TLB_LO1 # See what we got + mtc0 t0, COP_0_TLB_HI # restore PID MIPS_CPU_NOP_DELAY mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX @@ -408,7 +408,7 @@ *-------------------------------------------------------------------------- */ LEAF(Mips_TLBGetPID) - dmfc0 v0, COP_0_TLB_HI # get PID + mfc0 v0, COP_0_TLB_HI # get PID j ra and v0, v0, VMTLB_PID # mask off PID END(Mips_TLBGetPID) @@ -428,7 +428,7 @@ mfc0 v1, COP_0_STATUS_REG # save status register mtc0 zero, COP_0_STATUS_REG # disable interrupts - dmfc0 t4, COP_0_TLB_HI # Get current PID + mfc0 t4, COP_0_TLB_HI # Get current PID move t2, a0 mfc0 t1, COP_0_TLB_WIRED li v0, MIPS_KSEG0_START # invalid address @@ -440,14 +440,14 @@ MIPS_CPU_NOP_DELAY tlbr # obtain an entry MIPS_CPU_NOP_DELAY - dmfc0 a0, COP_0_TLB_LO1 + mfc0 a0, COP_0_TLB_LO1 and a0, a0, PG_G # check to see it has G bit bnez a0, 2f nop - dmtc0 v0, COP_0_TLB_HI # make entryHi invalid - dmtc0 zero, COP_0_TLB_LO0 # zero out entryLo0 - dmtc0 zero, COP_0_TLB_LO1 # zero out entryLo1 + mtc0 v0, COP_0_TLB_HI # make entryHi invalid + mtc0 zero, COP_0_TLB_LO0 # zero out entryLo0 + mtc0 zero, COP_0_TLB_LO1 # zero out entryLo1 mtc0 zero, COP_0_TLB_PG_MASK # zero out mask entry MIPS_CPU_NOP_DELAY tlbwi # invalidate the TLB entry @@ -456,7 +456,7 @@ bne t1, t2, 1b nop - dmtc0 t4, COP_0_TLB_HI # restore PID + mtc0 t4, COP_0_TLB_HI # restore PID mtc0 t3, COP_0_TLB_PG_MASK # restore pgMask MIPS_CPU_NOP_DELAY mtc0 v1, COP_0_STATUS_REG # restore status register