Date: Sat, 15 Nov 1997 20:21:24 +0000 From: "Pedro F. Giffuni" <giffunip@asme.org> To: multimedia@freebsd.org Subject: Info about CPQ Enhanced Business Au Message-ID: <346E0444.5E6C70B6@asme.org>
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Howdy,
Compaq has made available some information on the sound system
integrated in the latest Deskpro's. I have a Deskpro/i, with the older
(unenhanced) support, so this information is practically useless to me.
FWIW, this cards are supported by the latest OSS/Free for Linux.
http://www.4front-tech.com/ossfree/
I hope someone finds a good use for this.
Pedro.
__________Date: May 1994
Part Number: 002A/1093
The enhanced business audio interface is I/O mapped and has three types
of registers associated with it:
o Sound system setup registers that set up the audio interface for MWSS
compatibility.
o Audio configuration registers that configure the audio interface for
IRQ
and DMA.
o Audio operation registers that control the operation of the audio
interface.
The enhanced business audio is configurable to be MWSS compatible
without the need for additional drivers. This is a change from the audio
interface used in the Compaq Deskpro/i family, which required special
drivers for full MWSS compatibility.
Sound System Setup Registers
The audio interface is configured through four I/O addresses. Using bank
switching, seven registers (the eighth is reserved) are used for setting
up the audio interface. Table 7-2 lists the Sound System Setup
Registers,
which are described in the following paragraphs.
Table 7-2. Sound System Setup Registers
===========================================================================
Address Register R/W
===========================================================================
0C44h Audio Configuration R/W
0C45h FM Address Decode/MWSS ID R/W
0C46h FM Address Decode/Address ASIC ID R/W
0C47h FM Address Decode R/W
===========================================================================
Audio Configuration Register (0C44h, Read/Write)
This register controls the general configuration of the enhanced
business audio interface. Note that only bit <2> is present in both
banks and, in fact, is the only bit present in bank 1 at the 0C44h
address.
Bank 0 Value after reset = 01000000
BIT FUNCTION
----------------
7,6 Audio Revision Bits
00 = Compaq Business Audio
01 = Microsoft Sound System Compatible
(reset default)
10 = Reserved
11 = Reserved
5 No Wait State (NOWS-) Enable
0 = Disabled (reset default, DMA mode)
1 = Enabled (programmed I/O mode)
4 Microsoft Sound System Decode Enable
0 = Decoding disabled (reset default)
1 = Decoding enabled
3 FM Synthesis Decode Enable
0 = Decoding disabled (reset default)
1 = Decoding enabled
2 Bank Select
0 = Bank 0 (reset default)
1 = Bank 1
1.0 Microsoft Sound System Base Address
00 = 0530:0537h (reset default)
01 = 0604:060Bh
10 = 0F40:0F47h
11 = 0E80:0E87h
Bank 1 Value after reset = 00000000
BIT FUNCTION
----------------
7..3 Reserved - read 0s
2 Bank Select
0 = Bank 0 (reset default)
1 = Bank 1
1,0 Reserved - read 0s
FM Address Decode/MWSS ID Register (0C45h, Read/Write)
This register contains decode compare bits for the FM synthesis logic
and also contains the MWSS ID value.
Bank 0 Value after reset = 10001000
BIT FUNCTION
----------------
7..1 FM Synthesis Decode Compare Bits <7:1>.
(reset default value = 88h)
0 PBIC Power Control Bit:
0 = Powered up
1 = Powered down
Bank 1 Value after reset = 00010001
BIT FUNCTION
----------------
7..2 MWSS ID - 04h. Any read from 530-533h should yield these
bits, but as D5-D0 when read by MWSS.
1,0 Reserved.
FM Address Decode/Address ASIC Revision Register (0C46h Read/Write)
This register contains decode compare bits for the FM synthesis logic
and also contains the revision number for the audio addressing ASIC.
Bank 0 Value after reset = 00000011
BIT FUNCTION
----------------
7..0 FM Synthesis Decode Compare Bits <15:8>.
(reset default value = 03h)
Bank 1 Value after reset = 00010001
BIT FUNCTION
----------------
7..0 Audio Addressing ASIC ID. Value = 11h minimum.
FM Address Decode Register (0C47h Read/Write)
This register (in bank 0) sets the decode range for the FM synthesis
logic.
The bank 1 register is reserved.
Bank 0 Value after reset = 01111100
BIT FUNCTION
----------------
7 FM Synth. Decode Compare Bits <15:12> Enable.
0 = Do not use bits <15:12>
1 = Use bits <15:12>
6 FM Synth. Decode Compare Bits <11:10> Enable.
0 = Do not use bits <11:10>
1 = Use bits <11:10>
5 FM Synth. Decode Compare Bit <5> Enable.
0 = Do not use bit <5>
1 = Use bit <5>
4 FM Synth. Decode Compare Bit <4> Enable.
0 = Do not use bit <4>
1 = Use bit <4>
3 FM Synth. Decode Compare Bit <3> Enable.
0 = Do not use bit <3>
1 = Use bit <3>
2 FM Synth. Decode Compare Bit <2> Enable.
0 = Do not use bit <2>
1 = Use bit <2>
1 FM Synth. Decode Compare Bit <1> Enable.
0 = Do not use bit <1>
1 = Use bit <1>
0 General Purpose Bit 1 (GP1). Used to mute audio with XCTL0 from
the PBIC.
Bank 1 Value after reset = 00000000
BIT FUNCTION
----------------
7..0 Reserved.
Audio Configuration Registers
The audio configuration registers (listed in Table 7-3) are used to
select IRQ and DMA and also allow complete disabling/enabling of the
audio interface.
Table 7-3. Audio Configuration Registers
===========================================================================
Address Register R/W
===========================================================================
0530h-0533h Audio IRQ/DMA Mapping WO
0530h-0533h Audio IRQ/DMA Status RO
0C57h Audio Disable R/W
===========================================================================
Audio IRQ/DMA Mapping Register (0530h, Write Only)
This write-only register is used to select the IRQ and DMA to be used by
the audio interface. Under MWSS control, a write to any one the first
four addresses in the selected base address range will alias to the
first address; i.e., a write to 0531h, 0532h, or 0533h will place the
contents into 0530h.
BIT FUNCTION
----------------
7,6 Reserved - write 0
5..3 IRQ Source Sense:
0 = Normal operation. IRQ selected by IRQ select word is
enabled. Bit 6 of the read-only audio status register will
sense a PBIC or an FM synthesis interrupt.
1 = All system IRQ lines are tri-stated. MWSS polls the IRQ
selected by bits 5..3 for availability. The PBIC and FM
interrupts will not figure in IRQ generation.
2..0 DMA Select. These bits select the DMA channel MWSS will use.
000 = playback + capture disabled
001 = playback 0, capture disabled
010 = playback 1, capture disabled
011 = playback 3, capture disabled
100 = playback disabled, capture 1
101 = playback 0, capture 1
110 = playback 1, capture 0
111 = playback 3, capture 0
Audio IRQ/DMA Status Register (0530h, Read Only)
This read-only register is used to read what DMA channels are available
and the status of IRQ sensing as determined by the write-only IRQ/DMA
mapping register previously described. Under MWSS control, a read to
any one the first four addresses in the selected base address range will
alias to the first address; i.e., a read to 0531h, 0532h, or 0533h will
yield the contents of 0530h.
BIT FUNCTION
----------------
7 DMA channels available. (MWSS returns the state of SBHE-).
0 = DMA channels 0, 1, 3 and IRQs 7, 9, 10, and 11 are
available.
1 = DMA channels 1 and 3 and IRQs 7 and 9 are available.
6 IRQ Sense:
If IRQ/DMA mapping register bit <6> = 0 (normal operation):
0 = PBIC or FM synthesis interrupt is not active.
1 = PBIC or FM synthesis interrupt is active.
If IRQ/DMA mapping register bit <6> = 1 :
0 = Selected system IRQ line is in use.
1 = Selected system IRQ line is free.
5..0 MWSS ID bits. MWSS uses these six bits to read the value
written to 0C45h (bank 1) bits <7..2>.
Bit <6> of the write-only IRQ/DMA mapping and read-only IRQ/DMA status
registers allow for an FM synthesis interrupt to be detected. Software
must, however, determine whether the PBIC or the FM synthesis generated
the interrupt.
Audio Disable Register (0C57h Read/Write)
Bit <0> of this register can be used to disable the enhanced business
audio interface. Bits <7..1> are reserved.
Value after reset = 00000001
BIT FUNCTION
----------------
7..1 Reserved - R/W 0s
0 Audio Enable/Disable
0 = Enabled
1 = Disabled (reset default)
When bit <0> is set, decoding of the following addresses is inhibited:
Address Function
------- --------
0388h-038Bh FM synthesis
0530H-0537h audio configuration and operation (primary)
0604h-060Bh audio configuration and operation (alternate)
0C44h-0C47h sound system setup
0E80h-0E87h audio configuration and operation (alternate)
0F40h-0F47h audio configuration and operation (alternate)
Audio Operation Registers
The audio operation registers control the operation of the FM synthesis
logic and PBIC. Consequently, the registers can be classified as the FM
Synthesis Control Registers and the PBIC Control Registers.
FM Synthesis Control Registers
The FM synthesis logic is typically mapped at 0388h-038Bh. The YMF262
synthesizer component is used, which contains a total of 243 control
registers divided into two banks. The YMF262's control registers are
accessed by first writing the address of the control register to 0388h
(for bank 0) or 038Ah (for bank 1) followed by writing the data to
either 0389h or 038Bh. If a succeeding data byte is destined for the
same control register, that control register's address need not be
re-written.
Basically, FM synthesis is a write-only operation; only one read, for
status, is permitted. Table 7-4 lists the mapping of the FM synthesis
logic.
Table 7-4. FM Synthesis Mapping
===========================================================================
Address Register R/W
===========================================================================
0388h FM Synthesizer Register Address Write (Bank 0) WO
0388h FM Synthesizer Status Register RO
0389h FM Synthesizer Register Data Write WO
038Ah FM Synthesizer Register Address Write (Bank 1) WO
038Bh FM Synthesizer Register Data Write WO
===========================================================================
Table 7-5 lists the control registers for FM synthesis. Refer to the
data sheet for the YMF262 for detailed register information.
Table 7-5. FM Synthesis Control Registers
===========================================================================
Address Bank 0 Function Bank 1 Function
===========================================================================
01h Test - all 0s Test - all 0s
---------------------------------------------------------------------------
02h Timer 1 Not Used
---------------------------------------------------------------------------
03h Timer 2 Not Used
---------------------------------------------------------------------------
04h Timer Mask/Timer Start 4-Operator
Configuration
---------------------------------------------------------------------------
05h Not Used 4-Operator
Enable
---------------------------------------------------------------------------
08h Key Scale (KSR) Number Determiner Not Used
---------------------------------------------------------------------------
20h-35h Amplitude Modulation (tremolo),
Vibrato, EG Type, KSR, Multifrequency Same as bank 0
---------------------------------------------------------------------------
40h-55h Key Scale Level, Tone Level Same as bank 0
---------------------------------------------------------------------------
60h-75h Attack Rate, Decay Rate Same as bank 0
---------------------------------------------------------------------------
80h-95h Sustain Level, Release Rate Same as bank 0
---------------------------------------------------------------------------
A0h-A8h Frequency Number Same as bank 0
---------------------------------------------------------------------------
B0h-B8h Key On, Block Octave, Frequency Number Same as bank 0
---------------------------------------------------------------------------
BDh Depth. of Amplitude Modulation
(tremolo)/Vibrato, Rhythm Mode Not Used
---------------------------------------------------------------------------
C0h-C8h Stereo Left/Right, Feedback,
Connection (oscillator configuration) Same as bank 0
---------------------------------------------------------------------------
E0h-F5h Wave Select Same as bank 0
===========================================================================
PBIC Control Registers
The PBIC ASIC is typically mapped at the base address 0534h. The PBIC
contains a number of control registers that are indirectly addressed
through I/O locations 0534h and 0535h. Tables 7-5 and 7-6 list the
PBIC's
directly and indirectly addressed registers, respectively.
Table 7-6. PBIC Mapping
===========================================================================
Address Register R/W
===========================================================================
0534h PBIC Register Index (refer to Table 7-7) R/W
0535h PBIC Register Function (refer to Table 7-7) R/W
0536h PBIC Status R/W
0537h PBIC Programmed I/O Data R/W
===========================================================================
Table 7-7. PBIC Control Registers
===========================================================================
Index Function Index Function
===========================================================================
00h Left Input Control 08h Data Format
01h Right Input Control 09h Interface Configuration
02h Left Aux. 1 Input Control 0Ah Pin Control
03h Right Aux. 1 Input Control 0Bh Test and Configuration
04h Left Aux. 2 Input Control 0Ch Miscellaneous
Information
05h Right Aux. 2 Input Control 0Dh Loopback Control
06h Left Output Control 0Eh Upper Base Count
07h Right Output Control 0Fh Lower Base Count
===========================================================================
Index Register (534h, 608h, E84, or F44, Read/Write)
This register holds the value of 01000000 when the audio ASIC has left
the initialization state following a reset.
BIT FUNCTION
----------------
7 Initialization (RO)
0 = Audio ASIC is ready to handle digital I/O
1 = Audio ASIC is being initialized and digital I/O is disabled
6 Mode Change Enable
0 = Data Format and Data Interface registers cannot be changed.
1 = Data Format and Data Interface registers can be changed and
audio activity is inhibited
5 Transfer Request Disable
0 = DMA transfers are enabled
1 = DMA transfers are disabled (DMA transfers possible only if
Status register bit <0> is 0).
4 Reserved
3..0 Index Address. These bits define the address of the audio
register accessed by Data Register. (Refer to Table 7-6)
Data Register (535h or 609h, Read/Write)
This register holds the data byte of the register indexed by the Index
Register (Refer to Table 7-6). This register cannot be written to during
initialization of the audio ASIC and will, during that time, read
10000000 (80h).
Status Register (536h or 60Ah, Read/Write)
BIT FUNCTION
----------------
7 Capture Byte Ready (read only)
0 = Lower byte ready
1 = Upper or 8-bit mode byte ready
6 Capture Left/Right Sample Ready (read only)
0 = Right channel data
1 = Left channel or mono data
5 Capture Data Ready (read only)
0 = Data is stale (do not reread)
1 = Data is fresh (has not been read)
4 Sample Overrun (read only). When set, this bit indicates that
a sample was not processed in time and that either a capture
overrun or a playback underrun has occurred. Note that if both
capture and playback have been enabled, the activity that sets
this
bit cannot be determined.
3 Playback Byte Required (read only).
0 = Lower byte needed
1 = Upper or 8-bit mode byte
2 Playback Sample Required (read only).
0 = Right channel data needed
1 = Left channel or mono data needed
1 Playback Data Ready (read only).
0 = Data is fresh (do not overwrite)
1 = Data is stale, ready for new write
0 Interrupt Status (of audio ASIC). This bit is cleared by a write
of any value to this register. Bit <1> of the Pin Control
Register
determines whether the INT pin of the audio ASIC reflects the
state
of this bit.
0 = Interrupt pin inactive
1 = Interrupt pin active
Programmed I/O Data Register (537h or 60Bh, Read/Write)
This is actually a pair of registers (one read only, the other write
only) mapped at the same address. During audio ASIC initialization, this
address cannot be written to and will read 10000000 (80h).
A read to the address fetches a byte of digital audio data held in the
Capture Data Register. Each read increments the audio ASIC state machine
so that the following read will fetch the next byte of the sample. (The
next byte to be read can be determined through the Status Register.) If
the Capture Data Register does not receive the first byte of the next
sample from the ADCs, then the next read will fetch the most significant
byte of the last sample.
A write to the address places a byte of digital audio data into the
Playback Data Register. Each write increments the audio ASIC state
machine so that the following write will be of the correct byte of the
sample. When all bytes of a sample have been written, additional writes
are ignored until the current sample is transferred to the DACs and the
state machine is reset.
Left Input Control Register (Index 00h to 534h or 608h, Data to 535h or
609h, Read/Write)
See register bit map below.
Right Input Control Register (Index 01h to 534h or 608h, Data to 535h or
609h, Read/Write)
See register bit map below.
BIT FUNCTION
----------------
7,6 Input Source
00 = Line selected
01 = Auxiliary 1 selected
10 = Microphone selected
11 = Line output loopback selected
5 Input Mic Gain Enable. When set, enables a 20 db gain of the
left mic input signal.
4 Reserved
3..0 Input Gain in increments of 1.5 db (Range of 0 to +22.5db)
State after reset = 00000000
Auxiliary Number 1 Left Channel Input Control Register (Index 02h to
534h or 608h, Data to 535h or 609h, Read/Write)
See register bit map below.
Auxiliary Number 1 Right Channel Input Control Register (Index 03h to
534h or 608h, Data to 535h or 609h, Read/Write)
See register bit map below.
Auxiliary Number 2 Left Channel Input Control Register (Index 04h to
534h or 608h, Data to 535h or 609h, Read/Write)
See register bit map below.
Auxiliary Number 2 Right Channel Input Control Register (Index 05h to
534h or 608h, Data to 535h or 609h, Read/Write)
See register bit map below.
BIT FUNCTION
----------------
7 Channel Mute. When set, mutes the auxiliary channel signal.
6..4 Reserved
3..0 Channel Attenuate Control. LSB represents -1.5 db of
attenuation.
(range of 0 to -22.5 db)
State after reset = 10000000
Left Output Channel Control Register (Index 06h to 534h or 608h, Data to
535h or 609h, Read/Write)
See register bit map below.
Right Output Channel Control Register (Index 07h to 534h or 608h, Data
to 535h or 609h, Read/Write)
See register bit map below.
BIT FUNCTION
----------------
7 Output Mute. When set, the output channel is muted.
6 Reserved
5..0 Output Attenuate Control. The LSB represents 1.5 db.
(Full attenuation is at -96 db) Range of 0 to -96db
State after reset = 10000000
Data Format Register (Index 08h to 534h or 608h, Data to 535h or 609h,
Read/Write)
This register controls the format of digital audio data. The contents of
this register cannot be changed unless bit <6> of the Index Address
Register is set. Writes to this register at any other time will have no
effect.
BIT FUNCTION
----------------
7 Reserved
6,5 Format Select
00 = 8-bit unsigned linear
01 = u-law companded
10 = 16-bit signed, linear
11 = A-law companded
4 Stereo/Mono Select
0 = Mono
1 = Stereo
3..0 Sample Rate Select. Bit <0> determines the clock input
to be used. Bits <3..1> determine the value used to divide the
selected clock frequency resulting in the sample rate listed
below.
0000 = 8.00 KHz 1000 = N/A
0001 = 5.51 KHz 1001 = 37.8 KHz
0010 = 16.0 KHz 1010 = N/A
0011 = 11.2 KHz 1011 = 44.1 KHz
0100 = 27.4 KHz 1100 = 48.0 KHz
0101 = 18.9 KHz 1101 = 33.0 KHz
0110 = 32.0 KHz 1110 = 9.6 KHz
0111 = 22.0 KHz 1111 = 6.6 KHz
State after reset = 00000000
Interface Configuration Register (Index 09h to 534h or 608h, Data to
535h or 609h, Read/Write)
Bits <7..2> of this register can only be written to while bit <6> of the
Index Address Register is set. Bits <1,0>, however, are writeable
without having to set/bit <6> of the Index Address Register.
BIT FUNCTION
----------------
7 Capture Transfer Type
0 = DMA transfers only
1 = Programmable I/O only
6 Playback Transfer Type
0 = DMA transfers only
1 = Programmable I/O only
5,4 Reserved
3 Autocalibrate Enable. When set, the audio ASIC is allowed to
automatically calibrate itself when returning from a powerdown
or
when the Mode Change Enable bit (bit 6 of the Index Address
Register) is being asserted.
2 DMA Channel Mode Select.
0 = Dual DMA channel mode
1 = Single DMA channel mode
1 Capture Enable *
0 = Capture disabled
1 = Capture enabled
0 Playback Enable *
0 = Playback disabled
1 = Playback enabled
State after reset = 00010000
* These bits can be changed without having to set bit 6 of the Index
Register.
Pin Control Register (Index 0Ah to 534h or 608h, Data to 535h or 609h,
Read/Write)
Bit <1> of this register enables, when set, the interrupt output pin of
the audio ASIC. The interrupt pin goes active (high) when the number of
samples programmed into the Base Count Register is reached. All other
bits in this register are reserved.
Text and Initialization Register (Index 0Bh to 534h or 608h, Data to
535h or 609h, Read/Write)
BIT FUNCTION
----------------
7 Capture Overrun. When set, indicates that capture data has not
been read by the CPU. A new sample will not be accepted until
the
present sample has been read and this bit is cleared.
6 Playback Underrun. When set, indicates that playback data has
not arrived in time to be read, in which case the previous
sample
is read again.
5 Autocalibrate In Progress. When set, indicates that
autocalibration
is in progress.
4 DRQ Status. When active, indicates that either a capture data
or playback data sample is ready for processing.
3,2 Overrange Right Detect. These bits determine the overrange
on the right input channel
00 = Less than -1 db under
01 = Between -1 db and 0 db under
10 = Between 0 db and 1 db over
11 = Greater than 1 db over
1,0 Overrange Left Detect. These bits determine the overrange
on the left input channel
00 = Less than -1 db under
01 = Between -1 db and 0 db under
10 = Between 0 db and 1 db over
11 = Greater than 1 db over
Miscellaneous Information Register (Index 0Ch to 534h or 608h, Data to
535h or 609h, Read/Write)
NOTE: This register contains bits that allow for future expansion of
ASIC
functions. Writing to this register may cause unpredictable
results.
BIT FUNCTION
----------------
7..4 Reserved
3..0 ASIC Revision ID (read only).
State after reset = 00001000
Loopback Control Register (Index 0Dh to 534h or 608h, Data to 535h or
609h, Read/Write)
BIT FUNCTION
----------------
7..2 Loopback Attenuation. These bits determine the amount of
attenuation in the loopback from ADC to DAC in 1.5 db steps.
Range
of 0 to -96db.
1 Reserved
0 Loopback Enable. When set, enables the ADC output to be mixed
(looped back) with other data to the DAC.
DMA Base Count Registers (534h or 608h, Index 0Eh and 0Fh, Read/Write)
The audio ASIC contains DMA count logic to notify the CPU when a DMA
transfer is required. The DMA Base Count Registers hold the number of
samples to be processed before an interrupt will be sent to the CPU.
This value, held in the Upper Base Count Register (index 0Eh) and the
Lower Base Count Register (index 0Fh) is loaded into the 16-bit Current
Count Register at the start of each sampling cycle.
As each sample is received (assuming either playback or capture has been
enabled), the Current Count Register is decremented until zero is
reached.
The next sample will generate the interrupt and reload the Current Count
Register with the value held in the Base Count Registers. Note that the
Current Count Register is not accessible (cannot be read) by the CPU.
Only the programmed base count can be read.
When programming the Base Count Registers, write (the LSB) to the Lower
Base Count Register first. Writing (the MSB) to the Upper Base Count
Register automatically loads the value from both Base Count Registers to
the Current Count Register.
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