Date: Sat, 1 Oct 2011 17:38:30 +0530 From: "Jayachandran C." <jchandra@freebsd.org> To: Adrian Chadd <adrian@freebsd.org> Cc: Alexander Motin <mav@freebsd.org>, freebsd-mips@freebsd.org Subject: Re: svn commit: r225892 - head/sys/mips/mips Message-ID: <CA%2B7sy7DFCMxo-2bJwBJcSEJf7ewG7Y=XwdgKXkhpRyDXQpvsYA@mail.gmail.com> In-Reply-To: <CAJ-Vmon_a_zLZmEGqwFaYaobjYFE2i1u2Viq3QD5dw4wpNNURA@mail.gmail.com> References: <201110010556.p915uQH6003016@svn.freebsd.org> <CA%2B7sy7BiRvTB79H9=y%2BS4jQ=%2BboW1bcDJn%2BBULMmJU9KLLVJ5A@mail.gmail.com> <CAJ-VmokAsDpjJLt%2BVJ2gDGX%2BiMAwZvL2TPaaAD_LRm-Yyquxig@mail.gmail.com> <CA%2B7sy7D6h5a08Q6yNfX6xSqwabDLzE5GLu5aV3fCMYQKn_4AoQ@mail.gmail.com> <CAJ-Vmon32cVEVvC=3WJVmDkCUdyLWyec3sqU-ifzspVSPxedfg@mail.gmail.com> <CAJ-Vmomsq5PQzbCBmWob5juB9EqdcEoYV%2B9vwYjnJQYTo_%2B4kw@mail.gmail.com> <CAJ-Vmon_a_zLZmEGqwFaYaobjYFE2i1u2Viq3QD5dw4wpNNURA@mail.gmail.com>
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Hi Adrain, On Sat, Oct 1, 2011 at 4:01 PM, Adrian Chadd <adrian@freebsd.org> wrote: > Just FYI, the MIPS24K software users manual, section 9.2.1: > > > 9.2.1 Wait IE Ignore > A feature is included in the core that simplifies the task of using > the WAIT instruction in the idle loop of an OS. The WAIT instruction > is typically in block of code where the OS first checks to see if > there is any pending work and if there is not, it will execute the > WAIT as shown below. > ... > > There is a tricky race condition present in this code. If an interrupt > arrives between the pending check and the WAIT instruction, the > service routine will return and execute the WAIT and go to sleep. > However, the interrupt may have been enabling some pending work to be > done in the =91bottom-half=92 processing. If the core goes back to sleep, > this pending work will not be done until the next interrupt arrives. > > The OS can check to see if the interrupt was signalled in this window > and adjust the EPC value to before the pending check, but this > involves a fair amount of work. Linux code seems to have this solution, i.e in the interrupt handler, compare the EPC with the r4_wait function's address before the 'wait' and then fixup EPC if needed. > The Wait IE Ignore feature enables a > simpler solution for the race con- dition. With this feature, a WAIT > condition will be terminated by an active interrupt signal, even if > that signal is pre- vented from causing an interrupt by StatusIE being > clear or TCStatusIXMT being set. This allows interrupts to be disabled > in this section of code while still allowing the WAIT to complete. Thanks for finding this. > That's likely a good solution for my platform, if it actually is > implemented for my core. Would you mind seeing if XLR has something > similar? I'll code this up tonight/tomorrow and see if I can coax my > mips24k cores to work correctly. Looks like I will have to implement the EPC fixup solution for XLR. But in the end I think probably we will have two implementations, one for the processors which can safely wait with interrupts off without the scheduling latency, and the other for platforms that need the EPC fixup. JC.
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