Date: Mon, 8 Aug 2011 22:17:34 +0200 From: Robert Millan <rmh@debian.org> To: freebsd-mips@freebsd.org Subject: [PATCH] missing bus_alloc_resouce() calls for i8259 Message-ID: <CAOfDtXO8DEjJKm3PZ_sUrr_X2%2Bh=bGdbuV2RUSpGSaGp7ExEag@mail.gmail.com>
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--90e6ba613ad036d55604aa042315 Content-Type: text/plain; charset=UTF-8 Attached patch fixes this problem when booting the MALTA flavour on QEMU: le0: <AMD PCnet-PCI> irq 0 at device 11.0 on pci0 le0: Lazy allocation of 0x20 bytes rid 0x10 type 4 at 0x20 qemu: hardware error: register_ioport_write: invalid opaque >From QEMU side, it appears that this I/O allocation is using the wrong address: 0x20 is reserved for the i8259 controller. >From FreeBSD kernel side, it appears that 0x20 is assigned to le driver because it hasn't been allocated by anybody else. i8259 is hooked to PCI bus on MALTA (or at least on QEMU/MALTA), but there's no corresponding bus_alloc_resource() call. So I've added bus_alloc_resource() calls to register the i8259 as a child of GT64120 PCI bridge. It appears to work, as QEMU now breaks when allocating le ports at 0x40 rather than 0x20: le0: <AMD PCnet-PCI> irq 0 at device 11.0 on pci0 le0: Lazy allocation of 0x20 bytes rid 0x10 type 4 at 0x40 qemu: hardware error: register_ioport_write: invalid opaque 0x40 is for i8254 controller. I could not find code to use this controller, but looking at platform_start() for MALTA I assume time is tracked by CPU count register without any external time source (not even for calibration! is that so?), and therefore i8254 is not used. Is there supposed to be a bus_alloc_resource() explicitly for i8254 too? I'm not sure if my patch is the right approach. In case it is, I know it's a bit kludgy; if you're interested, I could clean it up for your consideration. I'd propose adding a new function that takes care of i8259 stuff separately from gt_attach(), including bus_alloc_resource() registration and the register initialization above that. -- Robert Millan --90e6ba613ad036d55604aa042315 Content-Type: text/x-patch; charset=US-ASCII; name="006_mips_i8259_alloc.diff" Content-Disposition: attachment; filename="006_mips_i8259_alloc.diff" Content-Transfer-Encoding: base64 X-Attachment-Id: f_gr3vrkuu0 LS0tIGEvc3lzL21pcHMvbWFsdGEvZ3RfcGNpLmMKKysrIGIvc3lzL21pcHMvbWFsdGEvZ3RfcGNp LmMKQEAgLTQwMSw3ICs0MDEsMjIgQEAKIAl9CiAKIAkvKiBJbml0aWFsaXplIG1lbW9yeSBhbmQg aS9vIHJtYW5zLiAqLwotCWRldmljZV9hZGRfY2hpbGQoZGV2LCAicGNpIiwgYnVzbm8pOworCXsK KwkJZGV2aWNlX3QgY2hpbGQ7CisJCWludCByaWQ7CisJCXZvaWQgKnJlczsKKworCQljaGlsZCA9 IGRldmljZV9hZGRfY2hpbGQoZGV2LCAicGNpIiwgYnVzbm8pOworCisJCXJlcyA9IGJ1c19hbGxv Y19yZXNvdXJjZShjaGlsZCwgU1lTX1JFU19JT1BPUlQsICZyaWQsIElPX0lDVTEsIElPX0lDVTEg KyBJT19JQ1VTSVpFLCBJT19JQ1VTSVpFLCBSRl9BQ1RJVkUpOworCQlpZiAocmVzID09IE5VTEwp CisJCQlkZXZpY2VfcHJpbnRmKGNoaWxkLCAiY2Fubm90IGFsbG9jYXRlIHJlZ2lzdGVyc1xuIik7 CisKKwkJcmVzID0gYnVzX2FsbG9jX3Jlc291cmNlKGNoaWxkLCBTWVNfUkVTX0lPUE9SVCwgJnJp ZCwgSU9fSUNVMiwgSU9fSUNVMiArIElPX0lDVVNJWkUsIElPX0lDVVNJWkUsIFJGX0FDVElWRSk7 CisJCWlmIChyZXMgPT0gTlVMTCkKKwkJCWRldmljZV9wcmludGYoY2hpbGQsICJjYW5ub3QgYWxs b2NhdGUgcmVnaXN0ZXJzXG4iKTsKKwl9CisKIAlyZXR1cm4gKGJ1c19nZW5lcmljX2F0dGFjaChk ZXYpKTsKIH0KIAo= --90e6ba613ad036d55604aa042315--
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