Date: Sat, 15 Apr 1995 18:32:43 -0500 (CDT) From: bsinger@databank.com (Ben Singer) To: hackers@FreeBSD.org Subject: Re: class=bridge ???, OPTI Message-ID: <199504152332.SAA12584@databank.com > In-Reply-To: <199504141519.IAA01021@gndrsh.aac.dev.com> from "Rodney W. Grimes" at Apr 14, 95 08:19:42 am
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Rodney W. Grimes spake: > > > Is the `class=bridge' my problem, or just a bad motherboard/memory? > > No, but the opti chip set might be. Try setting the external cache > to ``write through mode'', if that doesn't fix this strange crashes > try setting the internal cache to ``write throught''. > > I have an Opti based board here, but it is not the ``super micro'' > version and I have to run it with the external cache in write through > mode. > > > FreeBSD 2.0.0-SNAP950322 #0: Sat Apr 8 10:39:53 1995 > > ben@koko.ben:/usr/src/sys/compile/BONES > > CPU: Pentium (Pentium-class CPU) 90 MHz Origin = "GenuineIntel" Id = 0x524 > > This is a Pentium 735\\90 or 815\\100 Stepping=4 Features=0x1bf FPU VME PSE MCE CX8 > > real memory = 16384000 (4000 pages) > > avail memory = 14999552 (3662 pages) > > Probing for devices on the ISA bus: > > sc0 at 0x60-0x6f irq 1 on motherboard > > sc0: VGA color <16 virtual consoles, flags=0x0> [cut] > > Probing for devices on the pci0 bus: > > configuration mode 1 allows 32 devices. > > pci0:16: OPTI, device=0xc822, class=bridge [not supported] > > > > Help appreciated... > > > > Ben > > > -- > Rod Grimes rgrimes@gndrsh.aac.dev.com > Accurate Automation Company Custom computers for FreeBSD > I tried write-through for external cache. cd /usr/ports/x11/gnuplot ; make was ok, but then make install immediately froze the computer (i was in X). I rebooted, and as soon as i logged in got a Fatal trap 12: page fault while in kernel mode ... Syncing disks... 20 20 20 20 20 [...] 20 giving up ...rebooted again, and right after npx0: INT 16 interface, another Fatal trap 12, "hit reset please" Hm. I disabled both caches to write this. There isn't an option for internal cache mode, here's what i have: AMIBIOS Release 122494 Hidden Refresh: Enabled CPU Address Pipeline Mode: Enabled DRAM Row Address Hold: 2 CLK DRAM Read CAS Pulse Width: 3 CLK DRAM Write CAS Pulse Width: 3 CLK DRAM RAS Precharge: 5 CLK Ext. Cache Mode: WrThru Ext. Cache to DRAM Post Write: Disabled Ext. Cache CAS Precharge: 2 CLK Ext. Cache Read Burst Mode: 4-3-3-3 Ext. Cache Write Burst Mode: 4-2-2-2 DRAM Base Memory: 640 KB DRAM Region A Control Mode: Disabled DRAM Region B Control Mode: Disabled Ben
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