Date: Mon, 15 Apr 1996 14:01:51 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: msmith@atrad.adelaide.edu.au (Michael Smith) Cc: peter@nmti.com, hackers@FreeBSD.ORG Subject: Re: Pentium fast copy? Message-ID: <199604152101.OAA09539@phaeton.artisoft.com> In-Reply-To: <199604140416.NAA11976@genesis.atrad.adelaide.edu.au> from "Michael Smith" at Apr 14, 96 01:46:21 pm
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[ ... Lai/Baker Pentium bcopy notes ... ] > Most of the implementations that have been thrown around here tend to > average at about 40M/sec. There have been some significantly faster under > certain specialised circumstances, but they tend to perform poorly on older > processors, or they fall foul of some of the caching policies imposed > by some motherboards, or they impose extra overhead elsewhere in the > system (the most common complaint is that context-switches have to become > more complex to handle the technique). > > I'd be really interested to see what sort of hardware they're using that > has 160M/sec of memory bandwidth. Unless they're running 100% static > RAM, I suspect they've never actually implemented their code on a practical > scale 8( I would suspect that a large part of the performance is in ensuring source and target addresses of the same quad alignment (using the 8 byte floating point copy) or the same dword alignment (using the integer register cache line prefetch method). The 160M/sec number is exceedingly optimististic. I would expect that we would be unable to see that performance until we could enable the alignment trap on a P5/P6 and fail unaligned memory access like a decent RISC chip, without causing the kernel to panic. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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