Date: Tue, 17 Sep 1996 14:55:24 +0930 (CST) From: Michael Smith <msmith@atrad.adelaide.edu.au> To: michaelv@MindBender.serv.net (Michael L. VanLoon -- HeadCandy.com) Cc: msmith@atrad.adelaide.edu.au, hardware@freebsd.org Subject: Re: RAM timings for Triton chipsets? Message-ID: <199609170525.OAA29451@genesis.atrad.adelaide.edu.au> In-Reply-To: <199609170500.WAA21788@MindBender.serv.net> from "Michael L. VanLoon -- HeadCandy.com" at Sep 16, 96 10:00:41 pm
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Michael L. VanLoon -- HeadCandy.com stands accused of saying: > > x2222 and x4444 mean how many cycles it takes to access memory for > each cycle of a burst read or write. The x means that the first > access is longer (typically something like 6 cycles). After the first > access, it can burst at a word for every 2 bus cycles (or as the case > is now, for ever 4 bus cycles). Hmm. It certainly isn't behaving 'much slower'... What sort of 'much' would you expect from that sort of change? > Michael L. VanLoon michaelv@MindBender.serv.net -- ]] Mike Smith, Software Engineer msmith@atrad.adelaide.edu.au [[ ]] Genesis Software genesis@atrad.adelaide.edu.au [[ ]] High-speed data acquisition and (GSM mobile) 0411-222-496 [[ ]] realtime instrument control (ph/fax) +61-8-267-3039 [[ ]] Collector of old Unix hardware. "Where are your PEZ?" The Tick [[
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