Date: Mon, 23 Dec 1996 23:39:18 -0800 From: Erich Boleyn <erich@uruk.org> To: dg@root.com Cc: smp@freebsd.org, haertel@ichips.intel.com, wscott@ichips.intel.com Subject: Re: I think we have the culprit!! (was -> Re: Eureka (maybe...) (was -> Re: P6 problem idea ) ) Message-ID: <E0vcRSI-0003hW-00@uruk.org> In-Reply-To: Your message of "Mon, 23 Dec 1996 22:05:33 PST." <199612240605.WAA27540@root.com>
next in thread | previous in thread | raw e-mail | index | archive | help
David Greenman <dg@root.com> writes: > >Erich Boleyn <erich@uruk.org> writes: ... > >I might be confused here, but as mentioned in the above comment, I > >thought this was implemented in the Pentium as well. Can someone > >who remembers better (or has the "Appendix H" equivalent released > >documentation) comment? > > Tge "PGE" feature doesn't appear to be present in the stepping 4 or > stepping 12 chips that I have here...so if the Pentium has the feature, > it must have been added only very recently. Well, if it wasn't in the mainstream Pentium CPUs, I don't think it would be in any of the newer ones. I think the only "new" features to the recent Pentium CPUs have been widely advertised (MMX, faster clocks...). Anyway, it seems reasonable that this is the main difference. I'll generate a cvs diff for the tree I have tomorrow morning (it conditionally compiles the Page Global stuff on not having SMP enabled, and adds the waiting of the other CPUs to the TLB shootdown... it doesn't synchronize the other CPUs *before* the page tables are changed, but that seems to be a much rarer problem, so getting this in as is is probably worthwhile). I must go to bed for now. -- Erich Stefan Boleyn \_ E-mail (preferred): <erich@uruk.org> Mad Genius wanna-be, CyberMuffin \__ (finger me for other stats) Web: http://www.uruk.org/~erich/ Motto: "I'll live forever or die trying"
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?E0vcRSI-0003hW-00>