Date: Thu, 17 Jul 1997 15:48:55 +0800 From: Peter Wemm <peter@spinner.dialix.com.au> To: Steve Passe <smp@csn.net> Cc: listuser <listuser@h2o.journey.net>, Chuck Robey <chuckr@Glue.umd.edu>, smp@FreeBSD.ORG Subject: Re: HEADS UP: EISA cards. Message-ID: <199707170748.PAA25589@spinner.dialix.com.au> In-Reply-To: Your message of "Wed, 16 Jul 1997 21:52:30 CST." <199707170352.VAA11792@Ilsa.StevesCafe.com>
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Steve Passe wrote: > Peter, > > > Again, remember that the feature that we are talking about (DMA Chaining) > > ... > > purpose of building a high performance system with multiple CPUs anyway. > > a related aspect of this is the functionality we gain by programming IO APIC > pin 0 as a 'regular' INT. Specifically, the 8259 becomes nothing more than a > buffer chip for the 8254 timer. It probably delays the clock INT by about > 10nsec, but this is probably pretty constant. And the timer returns > to being on vec[ 0 ] as a result. We might consider programming ALL systems > this way, whether they connect the timer to IO APIC pin 2 or not. This would > eliminate the "song and dance" I go thru using the vec[] array and the > indirections thru it to get to the hardware resumption routines. > This may well be why intel designed the PR440FX board to NOT have an IO APIC > pin 2 connection to the timer. They dont??? I thought the ones we were using did have the connection.. Hmm.. I see what you mean. Anyway, I think the reason it's not done is in order to support an extra steerable IDE interrupt (irq 15) with a limited number of pins on the chip package. After all, we all know how much the Wintel crowd love IDE. Dont forget the boards also have an ISA PNP Crystal SB16-clone chip onboard, how's that for priorities for a high-performance server board... > -- > Steve Passe | powered by > smp@csn.net | Symmetric MultiProcessor FreeBSD > > Cheers, -Peter
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