Date: Wed, 4 Feb 1998 01:59:40 -0500 (EST) From: "Adrian T. Filipi-Martin" <atf3r@cs.virginia.edu> To: Nate Williams <nate@mt.sri.com> Cc: FreeBSD Hackers List <hackers@FreeBSD.ORG> Subject: Re: Recompiling just kmem programs? Message-ID: <Pine.SOL.3.96.980204012148.22425D-100000@mamba.cs.Virginia.EDU> In-Reply-To: <199802021809.LAA28241@mt.sri.com>
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On Mon, 2 Feb 1998, Nate Williams wrote:
> > > > > # make obj && make depend && make && make install
>
> > > > 'make obj depend all install' oughta be enough for anyone.
> > > Actually, no.
> >
> > Would you care to elaborate? :)
> >
> > The general idea is that you want to make each of these targets, in
> > order, and stop everything if one of them fails. Doesn't 'make obj
> > depend all install' do just that?
>
> Yep, but if you do a 'make obj depend', the .depend file won't end up in
> the obj directory, simple because make doesn't 'reset' it's build
> environment to take advantage of the obj directory. In the same manner,
> if you do a 'make depend all', then make won't re-read the dependency
> files before making 'all' to determine if a file is out-of-date with
> respect to it's dependencies.
>
> This is just a generic problem with all Unix makes, and nothing new to
> BSD-Make. Normally it works fine since most targets don't depend on the
> ouytput of the previous target, but if they do there is a chance of not
> getting the correct results.
Actually, GNU make does not suffer from this problem and I use
this fact in most code that I write. If the dependency file does not
exist, GNU make can make it and then reread the dependency files before
continuing. Basically the included files become dependencies for the
makefile itself. Apparently the basic convention is derived from MACH's
makefiles.
Here's my template GNU makefile that accomplishes this:
#
# makefile (a GNU makefile)
# Time-stamp: <95/02/26 22:16:17 adrian>
#
# Adrian Filipi-Martin <adrian@virginia.edu>
#
#
SHELL = /bin/sh
CC = g++
CXX = ${CC}
CXXFLAGS = -g
CPPFLAGS =
HFILES = ${wildcard *.h}
CCFILES = ${wildcard *.cc}
OFILES = ${CCFILES:.cc=.o}
DFILES = ${CCFILES:.cc=.d} # Dependency files.
BINFILES = target
.PHONEY: clean vclean depend
# Manufacture depenency files on a per source file basis.
%.d: %.cc
$(SHELL) -ec '${CC} -M ${CPPFLAGS} $< \
| sed '\''s/$*\\.o[ :]*/& $@/g'\'' > $@'
%.d: %.c
$(SHELL) -ec '${CC} -M ${CPPFLAGS} $< \
| sed '\''s/$*\\.o[ :]*/& $@/g'\'' > $@'
all: ${BINFILES}
target: ${OFILES}
clean:
${RM} ${OFILES} ${DFILES} core.* *.core
vclean: clean
${RM} ${BINFILES}
depend:
@: # Execute but don't echo the sh null-statement.
# Include automatically generated dependencies at end,
# so that 'all' remains the default target.
-include ${DFILES}
The 'depend' targert is just there for convenience. Sometimes, I
like to do 'make depend' without making any .o files. It is enough,
however, to update the dependency files.
Adrian
--
adrian@virginia.edu ---->>>>| If I were stranded on a desert island, and
System Administrator --->>>| I could only have one OS for my computer,
Neurosurgical Visualzation Lab -->>| it would be FreeBSD. Think about it.....
http://www.nvl.virginia.edu/ ->| http://www.freebsd.org/
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