Date: Sun, 1 Mar 1998 01:18:49 +0100 (MET) From: Wolfgang Helbig <helbig@Informatik.BA-Stuttgart.DE> To: archie@whistle.com (Archie Cobbs) Cc: helbig@Informatik.BA-Stuttgart.DE, freebsd-isdn@FreeBSD.ORG Subject: Re: AVM A1 Setup bug on NetBSD? Message-ID: <199803010018.BAA00211@rvc1.informatik.ba-stuttgart.de> In-Reply-To: <199802282220.OAA08206@bubba.whistle.com> from Archie Cobbs at "Feb 28, 98 02:20:48 pm"
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> Wolfgang Helbig writes:
> > > > Feb 27 00:00:07 hal /netbsd: i4b-L2-i4b_tei_assign: tx TEI ID_Request
> > > > Feb 27 00:00:08 hal /netbsd: i4b-L2-i4b_T202_timeout: unit 0, N202 = 3
> > > > Feb 27 00:00:08 hal /netbsd: i4b-L2-i4b_tei_assign: tx TEI ID_Request
> > > > Feb 27 00:00:09 hal /netbsd: i4b-L2-i4b_T202_timeout: unit 0, N202 = 3
> > > > Feb 27 00:00:09 hal /netbsd: i4b-L2-i4b_tei_assign: tx TEI ID_Request
> > > > Feb 27 00:00:10 hal /netbsd: i4b-L2-i4b_T202_timeout: unit 0, N202 = 3
> > >
> > > Yes - this is very much likeley due to the interrupt handler not
> > > being called.
> >
> > The same happened on a FreeBSD SMP system. The workaround was
> > to MASK/UNMASK the ISAC/HSCX interrupts every time an ISAC command
> > is issued (see layer1/i4b_isac.c)
>
> Sounds like a case of the chip generating a level-sensitive interrupt
> and the board needing an edge. If a new interrupt becomes pending
^^^^^ and/or the PIC ?
> while you're in your interrupt routine, but before you've cleared
> the old interrupt condition, you must generate a new edge by masking
> and then unmasking all interrupts.
>
> Just a guess..
In fact the Siemens chips (ISAC, HSCX) both generate level-sensitive
interrupts and the PIC on a PC is programmed to be edge-sensitive.
That's why we have this MASK/UNMASK dance in the ISR in the first place.
We don't know so much about the board.
But on the SMP system not even *one* interrupt is delivered, so the
very first edge seems to be lost.
On the same hardware this edge is not lost if a uniprocessor kernel
is running.
Wolfgang
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