Date: Thu, 02 May 2002 00:37:47 -0700 From: Terry Lambert <tlambert2@mindspring.com> To: David Xu <bsddiy@yahoo.com> Cc: Andrew Gallatin <gallatin@cs.duke.edu>, freebsd-smp@freebsd.org Subject: Re: hlt when idle? Message-ID: <3CD0ECCB.A499BEFC@mindspring.com> References: <20020502014108.24342.qmail@web20908.mail.yahoo.com>
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David Xu wrote: > >> Is this because a HLTed CPU is not going to notice a new runnable job > >> (possibly migrating from another CPU) until it gets an interrupt to > >> wake it up? > > > >Partly. It's worse than that, if the system is relatively > >quiescent. Interrupts are routed with entry to the kernel, > >the system doesn't run in "virtual wire" mode, and it doesn't > >support seperately routing interrupts. > > You can not set "virtual wire" mode when SMP is enabled otherwise every CPU > will send interrupt ACK to PIC and make mess the PIC and lost other interrupts. UUUUUUUUGGGGGGHHHHHH! Excuse my dyslexia. Crap. Virtual wire mode is for providing a uniprocessor environemtn. I should have said "Symmetric I/O mode", almost everywhere I have ever said "virtual wire mode" in the past. The relevent section for my comment is "3.6.2.3 Symmetric I/O Mode", which says: Some MP operating systems operate in Symmetric I/O Mode. This mode requires at least one I/O APIC to operate. In this mode, I/O interrupts are generated by the I/O APIC. All 8259 interrupt lines are either masked or work together with the I/O APIC in a mixed mode. See Figure 3-5 for an overview of Symmetric I/O Mode. The APIC I/O unit has general-purpose interrupt inputs that can be individually programmed to different operating modes. The I/O APIC interrupt line assignments are system implementation specific. Refer to Chapter 4 for custom implementations and to Chapter 5 for default configurations. The hardware must support a mode of operation in which the system can switch easily to Symmetric I/O mode from PIC or Virtual Wire mode. When the operating system is ready to switch to MP operation, it writes a 01H to the IMCR register, if that register is implemented, and enables I/O APIC Redirection Table entries. The hardware must not require any other action on the part of software to make the transition to Symmetric I/O mode. It should be possible to set DMODE in the APIC ICR (Interrupt Command Register) to 100 and the DSH to 10 (broadcast) for the clock interrupt. This would result in the clock interrupt being sent as an NMI to all processors. This doesn't work if some idiot board designer ran the clock into the ISA PIC, and then ran the ISA PIC into the APIC, instead of running the clock into the APIC directly. THis would mean that you have to take all ISA interrupts or none the same as the clock interrupt, which is a crock. So in answer to Andrew's question: you can't get a broadcast for the clock interrupt on all Intel motherboards, only for some of them. -- Terry To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message
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