Date: Mon, 25 Aug 2003 11:07:44 -0700 From: Tim Kientzle <kientzle@acm.org> To: Garrett Wollman <wollman@khavrinen.lcs.mit.edu> Cc: current@freebsd.org Subject: Re: HTT on current Message-ID: <3F4A5070.6010508@acm.org> In-Reply-To: <200308251735.h7PHZ9bd094222@khavrinen.lcs.mit.edu> References: <JCEIKJMCANNPGKFKGLKLOENEDJAA.mikej@trigger.net> <3F4A1CE2.6080806@freebsd.org> <20030825164907.GA17503@dragon.nuxi.com> <3F4A43EA.9090500@tcoip.com.br> <200308251735.h7PHZ9bd094222@khavrinen.lcs.mit.edu>
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Garrett Wollman wrote: > The problem is that the P4 is not very wide to begin with, and it's very > hard to optimize well for that 23-stage pipeline. I'll say. I spent months tuning some assembly code for P3 and P4 and was quite disappointed that the P4 consistently required more CPU cycles for the same code. Only the P4s faster clock kept it from actually being slower than the P3. I attribute a lot of that to the P4s long pipeline. Tim
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