Date: Fri, 7 May 2004 03:18:47 +1000 (EST) From: Bruce Evans <bde@zeta.org.au> To: Bruce M Simpson <bms@spc.org> Cc: Andrew Gallatin <gallatin@cs.duke.edu> Subject: Re: 4.7 vs 5.2.1 SMP/UP bridging performance Message-ID: <20040507031253.Y21938@gamplex.bde.org> In-Reply-To: <20040506150754.GC27139@empiric.dek.spc.org> References: <FE045D4D9F7AED4CBFF1B3B813C85337045D8CB5@mail.sandvine.com> <20040506150754.GC27139@empiric.dek.spc.org>
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On Thu, 6 May 2004, Bruce M Simpson wrote: > On Thu, May 06, 2004 at 10:15:44AM -0400, Andrew Gallatin wrote: > > For what its worth, using those operations yeilds these results > > on my 2.53GHz P4 (for UP) > > > > Mutex (atomic_store_rel_int) cycles per iteration: 208 > > Mutex (sfence) cycles per iteration: 85 > > Mutex (lfence) cycles per iteration: 63 > > Mutex (mfence) cycles per iteration: 169 > > Mutex (none) cycles per iteration: 18 > > > > lfence looks like a winner.. > > Please be aware, though, that the different FENCE instructions are acting > as fences against different things. The NASM documentation has a good > quick reference for what each of the instructions do, but the definitive > reference is Intel's IA-32 programmer's reference manuals. They are also documented in amd64 manuals. Don't they all act as fences only on the same CPU, so they are no help for SMP? They are still almost twice as slow than full locks on Athlons, so hopefully they do more. Bruce
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