Date: Mon, 9 Jan 2006 13:27:40 -0500 From: Garance A Drosihn <drosih@rpi.edu> To: danial_thom@yahoo.com Cc: freebsd-questions@freebsd.org Subject: Re: Sparc vs i386 architecture Message-ID: <p0623091ebfe85a662a2b@[128.113.24.47]> In-Reply-To: <20060108201419.12325.qmail@web33305.mail.mud.yahoo.com> References: <20060108201419.12325.qmail@web33305.mail.mud.yahoo.com>
next in thread | previous in thread | raw e-mail | index | archive | help
At 12:14 PM -0800 1/8/06, Danial Thom wrote: >--- Wojciech Puchar <wojtek@tensor.3miasto.net> wrote: > > user Opteron/Athlon64 - better than both :) >> > > AMD made RISC-like architecture that just runs i386-like > > code (i386+more registers and few extra instructions, > > while lots of mostly-unused instructions emulated). > >Thats hilarious, a "reduced instruction set" >processor that has extra instructions! Good one! You should think of "RISC" as a "set of reduced instructions", and not a "reduced set of instructions". Even IBM's original RISC had a fairly large *number* of instructions, but fancier do-all instructions were removed in favor of instructions which did less, and thus could always complete in fewer CPU cycles. -- Garance Alistair Drosehn = gad@gilead.netel.rpi.edu Senior Systems Programmer or gad@freebsd.org Rensselaer Polytechnic Institute or drosih@rpi.edu
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?p0623091ebfe85a662a2b>