Date: Thu, 14 Dec 2006 20:55:18 +0000 From: Lars Heidieker <lars@heidieker.de> To: Martin Cracauer <cracauer@cons.org> Cc: freebsd-current@freebsd.org Subject: Re: Page table walk on TLB miss Message-ID: <606F3A60-8DFB-4564-A27E-F0E4F08AD29F@heidieker.de> In-Reply-To: <20061214193021.GA89046@cons.org> References: <20061214193021.GA89046@cons.org>
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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 14 Dec 2006, at 19:30, Martin Cracauer wrote: > Can somebody explain how the MMU walks the page table in RAM when > there is a TLB miss and where the FreeBSD code is that sets up the > tables? > > Is there actual OS code involved in the walking or does the OS just > set up the code and the MMU walks on it's own? > > Mostly interested in AMD64. > > In case of i386/amd64 the mmu walks the pagetables on it's on =20 (hardware page table walk). The walking is done with physical addresses starting at the physical =20 address stored in the cr3 register of the cpu. Yes other cpus do this completely different UltraSPARC eg has a =20 Software Table walk the cpu traps simply on aTSB miss and the rest is up to the OS. - -- Viele Gr=FC=DFe, Lars Heidieker lars@heidieker.de http://paradoxon.info - ------------------------------------ Mystische Erkl=E4rungen. Die mystischen Erkl=E4rungen gelten f=FCr tief; die Wahrheit ist, dass sie noch nicht einmal oberfl=E4chlich sind. -- Friedrich Nietzsche -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.5 (Darwin) iD8DBQFFgbo2cxuYqjT7GRYRAg0TAKCSr/jIUkS/Q2+bfst8LDbGEuZy7wCfVvkT OEJyC8xTCdfoOr1sfeYVEMk=3D =3D5TQh -----END PGP SIGNATURE-----
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