Date: Tue, 26 Feb 2008 07:41:55 -0700 (MST) From: "M. Warner Losh" <imp@bsdimp.com> To: rrs@freebsd.org Cc: perforce@freebsd.org Subject: Re: PERFORCE change 136240 for review Message-ID: <20080226.074155.906763861.imp@bsdimp.com> In-Reply-To: <200802261414.m1QEEvQx046221@repoman.freebsd.org> References: <200802261414.m1QEEvQx046221@repoman.freebsd.org>
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In message: <200802261414.m1QEEvQx046221@repoman.freebsd.org> "Randall R. Stewart" <rrs@freebsd.org> writes: : http://perforce.freebsd.org/chv.cgi?CH=136240 : : Change 136240 by rrs@rrs-mips2-jnpr on 2008/02/26 14:14:27 : : For octeon we use di/ei (this should be generalized : with a ifdef for mips64 or something). I was actually thinking that we just put the enable/disable instructions into the I/O routines directly, not hack the disable/enable intr routines and call them. Warner : Affected files ... : : .. //depot/projects/mips2-jnpr/src/sys/mips/mips/psraccess.S#4 edit : : Differences ... : : ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/psraccess.S#4 (text+ko) ==== : : @@ -130,17 +130,41 @@ : : : LEAF(disableintr) : +#ifdef TARGET_OCTEON : + .set mips64 : + .word 0x041626000 #di v0 : + : +#if defined(ISA_MIPS32) : + .set mips32 : +#elif defined(ISA_MIPS64) : + .set mips64 : +#elif defined(ISA_MIPS3) : + .set mips3 : +#endif : +#else : mfc0 v0, COP_0_STATUS_REG # read status register : nop : and v1, v0, ~SR_INT_ENAB : mtc0 v1, COP_0_STATUS_REG # disable all interrupts : MIPS_CPU_NOP_DELAY : and v0, SR_INT_ENAB # return old interrupt enable : +#endif : j ra : nop : END(disableintr) : : LEAF(set_intr_mask) : +#ifdef TARGET_OCTEON : + .set mips64 : + .word 0x041626020 #ei v0 : +#if defined(ISA_MIPS32) : + .set mips32 : +#elif defined(ISA_MIPS64) : + .set mips64 : +#elif defined(ISA_MIPS3) : + .set mips3 : +#endif : +#else : li t0, SR_INT_MASK # 1 means masked so invert. : not a0, a0 # 1 means masked so invert. : and a0, t0 # 1 means masked so invert. : @@ -151,6 +175,7 @@ : mtc0 v1, COP_0_STATUS_REG : MIPS_CPU_NOP_DELAY : move v0, v1 : +#endif : jr ra : nop : : @@ -167,6 +192,7 @@ : : END(get_intr_mask) : : + : : LEAF(getsr) : mfc0 v0, COP_0_STATUS_REG :
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