Date: Mon, 28 Apr 2008 10:01:30 -0600 (MDT) From: "M. Warner Losh" <imp@bsdimp.com> To: jhb@FreeBSD.org Cc: perforce@FreeBSD.org Subject: Re: PERFORCE change 140000 for review Message-ID: <20080428.100130.-957829052.imp@bsdimp.com> In-Reply-To: <200804250827.30083.jhb@freebsd.org> References: <200804132159.m3DLxs1b004670@repoman.freebsd.org> <200804250827.30083.jhb@freebsd.org>
next in thread | previous in thread | raw e-mail | index | archive | help
In message: <200804250827.30083.jhb@freebsd.org>
John Baldwin <jhb@FreeBSD.org> writes:
: On Sunday 13 April 2008 05:59:54 pm Warner Losh wrote:
: > http://perforce.freebsd.org/chv.cgi?CH=140000
: >
: > Change 140000 by imp@imp_lighthouse on 2008/04/13 21:59:12
: >
: > Allow MSI to be compiled out.
:
: Maybe __HAVE_MSI set in <machine/param.h>?
arm doesn't fit this model very well. Some of the arm machines have
MSI, while most don't. In the NetBSD "old school" model, you are
right, this is where we'd put things. However, since all arm things
are overloaded in arm (or armevb in new-school NetBSD), I believe that
these things need to move into the config files. We need to leverage
stuff like this into the std.FOO makefiles more than we have been.
I've done some test doodling with this for ARM, but more work is still
needed.
MIPS will be the same way. Octeon parts have MSI and PCI-e, but
ADM5120 parts don't have anything more than simple 33MHz PCI bus.
Also, this isn't anywhere near what I want to commit to the tree...
This is mostly an experiment. So I like the idea of having attributes
like this, I'm not sure machine/param.h is the right lace...
Warner
: > Affected files ...
: >
: > .. //depot/projects/arm/src/sys/dev/pci/pci.c#32 edit
: > .. //depot/projects/arm/src/sys/dev/pci/pci_pci.c#14 edit
: >
: > Differences ...
: >
: > ==== //depot/projects/arm/src/sys/dev/pci/pci.c#32 (text+ko) ====
: >
: > @@ -101,6 +101,7 @@
: > int reg, uint32_t data);
: > #endif
: > static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
: > +#ifdef MSI
: > static void pci_disable_msi(device_t dev);
: > static void pci_enable_msi(device_t dev, uint64_t address,
: > uint16_t data);
: > @@ -111,6 +112,7 @@
: > static int pci_msi_blacklisted(void);
: > static void pci_resume_msi(device_t dev);
: > static void pci_resume_msix(device_t dev);
: > +#endif
: >
: > static device_method_t pci_methods[] = {
: > /* Device interface */
: > @@ -155,12 +157,14 @@
: > DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
: > DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
: > DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
: > +#ifdef MSI
: > DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
: > DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
: > DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
: > DEVMETHOD(pci_release_msi, pci_release_msi_method),
: > DEVMETHOD(pci_msi_count, pci_msi_count_method),
: > DEVMETHOD(pci_msix_count, pci_msix_count_method),
: > +#endif
: >
: > { 0, 0 }
: > };
: > @@ -191,6 +195,7 @@
: > /* As does the Serverworks OSB4 (the SMBus mapping register) */
: > { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
: >
: > +#ifdef MSI
: > /*
: > * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
: > * or the CMIC-SL (AKA ServerWorks GC_LE).
: > @@ -215,7 +220,7 @@
: > * bridge.
: > */
: > { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
: > -
: > +#endif
: > { 0 }
: > };
: >
: > @@ -255,6 +260,7 @@
: > &pci_do_power_resume, 1,
: > "Transition from D3 -> D0 on resume.");
: >
: > +#ifdef MSI
: > static int pci_do_msi = 1;
: > TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
: > SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
: > @@ -269,6 +275,7 @@
: > TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
: > SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
: > &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
: > +#endif
: >
: > /* Find a device_t by bus/slot/function in domain 0 */
: >
: > @@ -544,6 +551,7 @@
: > cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
: > }
: > break;
: > +#ifdef MSI
: > #if defined(__i386__) || defined(__amd64__)
: > case PCIY_HT: /* HyperTransport */
: > /* Determine HT-specific capability type. */
: > @@ -592,6 +600,7 @@
: > PCIM_MSIX_BIR_MASK);
: > cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
: > break;
: > +#endif
: > case PCIY_VPD: /* PCI Vital Product Data */
: > cfg->vpd.vpd_reg = ptr;
: > break;
: > @@ -1081,6 +1090,7 @@
: > return (ENOENT);
: > }
: >
: > +#ifdef MSI
: > /*
: > * Support for MSI-X message interrupts.
: > */
: > @@ -1914,6 +1924,7 @@
: > return (msi->msi_msgnum);
: > return (0);
: > }
: > +#endif
: >
: > /* free pcicfgregs structure and all depending data structures */
: >
: > @@ -2194,6 +2205,7 @@
: > cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
: > status & PCIM_PSTAT_DMASK);
: > }
: > +#ifdef MSI
: > if (cfg->msi.msi_location) {
: > int ctrl;
: >
: > @@ -2216,6 +2228,7 @@
: > cfg->msix.msix_table_bar,
: > cfg->msix.msix_pba_bar);
: > }
: > +#endif
: > }
: > }
: >
: > @@ -2744,19 +2757,23 @@
: > pci_setup_intr(device_t dev, device_t child, struct resource *irq, int
: > flags, driver_filter_t *filter, driver_intr_t *intr, void *arg, void
: > **cookiep) {
: > +#ifdef MSI
: > struct pci_devinfo *dinfo;
: > struct msix_table_entry *mte;
: > struct msix_vector *mv;
: > + int rid;
: > uint64_t addr;
: > uint32_t data;
: > +#endif
: > void *cookie;
: > - int error, rid;
: > + int error;
: >
: > error = bus_generic_setup_intr(dev, child, irq, flags, filter, intr,
: > arg, &cookie);
: > if (error)
: > return (error);
: >
: > +#ifdef MSI
: > /*
: > * If this is a direct child, check to see if the interrupt is
: > * MSI or MSI-X. If so, ask our parent to map the MSI and give
: > @@ -2813,6 +2830,7 @@
: > return (error);
: > }
: > }
: > +#endif
: > *cookiep = cookie;
: > return (0);
: > }
: > @@ -2821,9 +2839,11 @@
: > pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
: > void *cookie)
: > {
: > +#ifdef MSI
: > struct msix_table_entry *mte;
: > + struct pci_devinfo *dinfo;
: > struct resource_list_entry *rle;
: > - struct pci_devinfo *dinfo;
: > +#endif
: > int error, rid;
: >
: > /*
: > @@ -2834,6 +2854,7 @@
: > */
: > if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
: > return (EINVAL);
: > +#ifdef MSI
: > rid = rman_get_rid(irq);
: > if (device_get_parent(child) == dev && rid > 0) {
: > dinfo = device_get_ivars(child);
: > @@ -2861,6 +2882,7 @@
: > pci_mask_msix(child, rid - 1);
: > }
: > }
: > +#endif
: > error = bus_generic_teardown_intr(dev, child, irq, cookie);
: > if (device_get_parent(child) == dev && rid > 0)
: > KASSERT(error == 0,
: > @@ -2900,6 +2922,7 @@
: > int subclass;
: > char *desc;
: > } pci_nomatch_tab[] = {
: > +#if 0
: > {PCIC_OLD, -1, "old"},
: > {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
: > {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
: > @@ -2978,6 +3001,7 @@
: > {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
: > {PCIC_DASP, -1, "dasp"},
: > {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
: > +#endif
: > {0, 0, NULL}
: > };
: >
: > @@ -3667,11 +3691,13 @@
: > pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
: > pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
: >
: > +#ifdef MSI
: > /* Restore MSI and MSI-X configurations if they are present. */
: > if (dinfo->cfg.msi.msi_location != 0)
: > pci_resume_msi(dev);
: > if (dinfo->cfg.msix.msix_location != 0)
: > pci_resume_msix(dev);
: > +#endif
: > }
: >
: > void
: >
: > ==== //depot/projects/arm/src/sys/dev/pci/pci_pci.c#14 (text+ko) ====
: >
: > @@ -79,11 +79,13 @@
: > DEVMETHOD(pcib_read_config, pcib_read_config),
: > DEVMETHOD(pcib_write_config, pcib_write_config),
: > DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
: > +#ifdef MSI
: > DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
: > DEVMETHOD(pcib_release_msi, pcib_release_msi),
: > DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
: > DEVMETHOD(pcib_release_msix, pcib_release_msix),
: > DEVMETHOD(pcib_map_msi, pcib_map_msi),
: > +#endif
: >
: > { 0, 0 }
: > };
: > @@ -242,8 +244,10 @@
: > }
: > }
: >
: > +#ifdef MSI
: > if (pci_msi_device_blacklisted(dev))
: > sc->flags |= PCIB_DISABLE_MSI;
: > +#endif
: >
: > /*
: > * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
: > @@ -554,6 +558,7 @@
: > return(intnum);
: > }
: >
: > +#ifdef MSI
: > /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
: > int
: > pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int
: > *irqs) @@ -611,6 +616,7 @@
: > bus = device_get_parent(pcib);
: > return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data));
: > }
: > +#endif
: >
: > /*
: > * Try to read the bus number of a host-PCI bridge using appropriate
: > config
:
:
:
: --
: John Baldwin
:
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?20080428.100130.-957829052.imp>