Date: Tue, 19 Nov 1996 23:15:56 -0700 From: Steve Passe <smp@csn.net> To: Barney Wolff <barney@databus.com> Cc: freebsd-smp@freebsd.org Subject: Re: 8259 vs APIC Message-ID: <199611200615.XAA22765@clem.systemsix.com> In-Reply-To: Your message of "Wed, 20 Nov 1996 00:17:00 EST." <329296a60.1bae@databus.databus.com>
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Hi, > If you'll pardon the naive opinion, it sounds to me as tho the 8259 > is expecting to handle edge-triggered interrupts (as we know to be > true, right?) but the APIC is really expecting level-triggered ints, > where the int will still be there when it's finally unmasked. it can be programmed on a pin by pin basis for either edge or level. --- > If that's true, I would be looking at a solution that kept the edge- > triggered ints on the 8259, as nothing will save you otherwise. So > what if you cut the rate of lost ints to one a week - that's utterly > unacceptable for a production machine. the "window of opportunity" can be closed with clever programming. I believe Bruce once commented that he thinks we could get away without masking edge trigger INTs entirely. Explaining why keeping the 8259s in the picture would take a small book to do properly, but the short version is that it would mean incredibly complex, inefficient code. Again, its an issue of priority vs. resources. Hopefully someone with more expertise than I in this area will step in and do "the good thing" with it. Or, sooner or later, I'll find time to tackle it. The SMP kernel runs for days without problems in its current state, so this is a low priority. The "giant locking" paradigm is the squeeky wheel right now. --- > I seem to recall that the APIC can be set for either edge or level, or > am I just fantasizing again? it can be set to either, BUT that 'either' has to be whatever the driving card is providing. In the case of ISA, thats active high/edge triggered. -- Steve Passe | powered by smp@csn.net | FreeBSD
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