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Date:      Sun, 30 Dec 2007 01:51:54 +0100
From:      Ivan Voras <ivoras@freebsd.org>
To:        freebsd-hackers@freebsd.org
Subject:   Re: Architectures with strict alignment?
Message-ID:  <fl6q3b$tro$1@ger.gmane.org>
In-Reply-To: <4776d1d7.zI7kRv9uFoaBNKnQ%perryh@pluto.rain.com>
References:  <fl4c8o$vpu$1@ger.gmane.org>	<20071229.122221.-432830441.imp@bsdimp.com> <4776d1d7.zI7kRv9uFoaBNKnQ%perryh@pluto.rain.com>

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perryh@pluto.rain.com wrote:

> The degree to which a PowerPC imposes a strict alignment requirement
> depends on both the particular processor model and the operation
> being performed.
>=20
> For ordinary integer arithmetic and logical operations, newer
> PPC processors tend to be more tolerant (although misalignment
> will typically carry a performance penalty).  For the semaphore
> primitives (lwarx/stwcx.) most PPC will require proper alignment
> and some will fault if the operand address is cache-inhibited
> (even though correctly aligned).

How would it behave in operations like

x =3D x + 1

where x is unaligned in memory? A RISC would have to load the value from
memory, increment it and store it.

I'm not particularly interested in slowdowns, just hard faults.


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