Date: Mon, 31 Dec 2007 13:33:27 +0200 From: Kostik Belousov <kostikbel@gmail.com> To: Erich Dollansky <oceanare@pacific.net.sg> Cc: Kip Macy <kip.macy@gmail.com>, Ivan Voras <ivoras@freebsd.org>, freebsd-hackers@freebsd.org Subject: Re: Architectures with strict alignment? Message-ID: <20071231113327.GN57756@deviant.kiev.zoral.com.ua> In-Reply-To: <4778B8A3.8040400@pacific.net.sg> References: <fl4c8o$vpu$1@ger.gmane.org> <47760132.5040306@pacific.net.sg> <b1fa29170712290014w780448bh8da93006a629b7b4@mail.gmail.com> <20071229111204.GX57756@deviant.kiev.zoral.com.ua> <20071230131056.GG57756@deviant.kiev.zoral.com.ua> <4778B8A3.8040400@pacific.net.sg>
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--rkfdwoJB1s8W8pdr Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Dec 31, 2007 at 05:38:43PM +0800, Erich Dollansky wrote: > Hi, >=20 > Kostik Belousov wrote: > >On Sat, Dec 29, 2007 at 01:12:04PM +0200, Kostik Belousov wrote: > >>On Sat, Dec 29, 2007 at 12:14:11AM -0800, Kip Macy wrote: > > > >I.e., it seems that gcc does not feel too guilty generating unaligned > >half-word writes on i386. :( >=20 > this should not be a problem inside a cache line. >=20 > If the access goes accross two cache lines and the other cache line is=20 > not in the cache, it becomes real difficult. >=20 > I can't tell you what the hardware actually does in this case. >=20 > It should read the second affected cache line into the cache. But what=20 > happens if the second affected cache line is blocked by another CPU=20 > while the current CPU blocks the first cache line? =46rom the manual, 253668, 7.1.1: Accesses to cacheable memory that are split across bus widths, cache lines, and page boundaries are not guaranteed to be atomic by the Intel Core 2 Duo, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, P6 family, Pentium, and Intel486 processors. The Intel Core 2 Duo, Intel Core Duo, Pentium M, Pentium 4, Intel Xeon, and P6 family processors provide bus control signals that permit external memory subsystems to make split accesses atomic; however, nonaligned data accesses will seriously impact the performance of the processor and should be avoided. I think we might get any half of the operation as a result. --rkfdwoJB1s8W8pdr Content-Type: application/pgp-signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.7 (FreeBSD) iD8DBQFHeNOGC3+MBN1Mb4gRAufQAKClWTHINgpi/1zY2srN/SAMrdTnJQCgtnzh P9T/Ljo3zDfDVRzZ8wnTFoM= =jND5 -----END PGP SIGNATURE----- --rkfdwoJB1s8W8pdr--
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