Date: Tue, 4 Oct 2011 10:45:05 +0800 From: Adrian Chadd <adrian@freebsd.org> To: Warner Losh <imp@bsdimp.com> Cc: "Jayachandran C." <jchandra@freebsd.org>, Kostik Belousov <kostikbel@gmail.com>, Alexander Motin <mav@freebsd.org>, "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org> Subject: Re: svn commit: r225892 - head/sys/mips/mips Message-ID: <CAJ-VmonPBD5Q-kPm%2BkZtK6_RssrtUAPgTPr=PEvUBdgjY55ycg@mail.gmail.com> In-Reply-To: <79147576-6E4F-46C9-8887-0847567A46A7@bsdimp.com> References: <CA%2B7sy7BiRvTB79H9=y%2BS4jQ=%2BboW1bcDJn%2BBULMmJU9KLLVJ5A@mail.gmail.com> <CAJ-VmokAsDpjJLt%2BVJ2gDGX%2BiMAwZvL2TPaaAD_LRm-Yyquxig@mail.gmail.com> <CA%2B7sy7D6h5a08Q6yNfX6xSqwabDLzE5GLu5aV3fCMYQKn_4AoQ@mail.gmail.com> <CAJ-Vmon32cVEVvC=3WJVmDkCUdyLWyec3sqU-ifzspVSPxedfg@mail.gmail.com> <CAJ-Vmomsq5PQzbCBmWob5juB9EqdcEoYV%2B9vwYjnJQYTo_%2B4kw@mail.gmail.com> <CAJ-Vmon_a_zLZmEGqwFaYaobjYFE2i1u2Viq3QD5dw4wpNNURA@mail.gmail.com> <CA%2B7sy7DFCMxo-2bJwBJcSEJf7ewG7Y=XwdgKXkhpRyDXQpvsYA@mail.gmail.com> <CAJ-VmokPFqS2oNWZ_mFSxy=0MXfgqtOcBHSQe%2BdYXvsLHAyGjQ@mail.gmail.com> <CAJ-VmomqmKPRHBCbt46_xXD0VoU47Q-vYWbAqCFaM635ZnOHWA@mail.gmail.com> <CAJ-VmomLbueaG3bmnT0WfeKaMSyXSNo80BWXqEe39z6x%2Bx8QoA@mail.gmail.com> <20111002110331.GF1511@deviant.kiev.zoral.com.ua> <CA%2B7sy7A%2Bq_N6Hr%2B3-tD=BJxmqtDgBeWF9HJCtopLF0RUz6hVyw@mail.gmail.com> <CA%2B7sy7Ax9SXSK1CyxuBNboktJxuQTMiu3D4NFmZSoq7-ipoQgA@mail.gmail.com> <CA%2B7sy7Cin5-cHcP-8_qYGhpEnAN9gw6S5ekXYK6Q3X9FREQggA@mail.gmail.com> <CAJ-Vmon7ydNeN9aubLNdpFJfMgY99FGj6JK07CuUEa8n3bHR2w@mail.gmail.com> <79147576-6E4F-46C9-8887-0847567A46A7@bsdimp.com>
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On 4 October 2011 10:39, Warner Losh <imp@bsdimp.com> wrote: >> Is one needed after the mtc0 after StartWaitSkip? > > I don't think it matters. =A0The COP0_SYNC is needed when you want to flu= sh the instruction pipeline so that changes to COP0 don't affect them 'rand= omly'. =A0However, in this case. =A0Either we're setting a bit that's alrea= dy set, which won't change anything, or we're setting a bit that's clear, w= hich will just delay the delivery of the interrupt a few cycles. =A0The rac= e where it happens before the wait instruction is handled by the rest of th= e patch. That makes sense. I'll try this patch out soon and let you all know how it = goes. Now, hm. How can I easily instrument whether the hardware is actually spending time in wait or not? Thanks, Adrian
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