Date: Fri, 9 Jul 2010 18:06:51 +0530 From: "Jayachandran C." <c.jayachandran@gmail.com> To: "M. Warner Losh" <imp@bsdimp.com>, rrs@lakerest.net, jmallett@freebsd.org, freebsd-mips@freebsd.org Subject: Re: Merging 64 bit changes to -HEAD - part 4 Message-ID: <AANLkTik8fBlxMyZ3AZETF_7DvlSpPsx2hozIWinRy0U0@mail.gmail.com> In-Reply-To: <AANLkTilFZ4zAKqGcDKie6og5Nhrh9PU_Ta3uDoq7yexA@mail.gmail.com> References: <AANLkTikSVi27V2UICgLvKd8Bk7v6tuGty9YX6-C6-21H@mail.gmail.com> <20100708.021250.1099368555950605809.imp@bsdimp.com> <AANLkTilFZ4zAKqGcDKie6og5Nhrh9PU_Ta3uDoq7yexA@mail.gmail.com>
next in thread | previous in thread | raw e-mail | index | archive | help
[-- Attachment #1 --]
On Thu, Jul 8, 2010 at 2:52 PM, Jayachandran C.
<c.jayachandran@gmail.com> wrote:
> On Thu, Jul 8, 2010 at 1:42 PM, M. Warner Losh <imp@bsdimp.com> wrote:
>> In message: <AANLkTikSVi27V2UICgLvKd8Bk7v6tuGty9YX6-C6-21H@mail.gmail.com>
>> "Jayachandran C." <c.jayachandran@gmail.com> writes:
[...]
>> : pmap-n64.patch
>> : The main n64 patch (from Juli's branch)
>> : This still uses the old 2-level page tables. But this adds other
>> : pmap code to support n64. I have re-arranged some of Juli's code to
>> : reduce #ifdefs.
>>
>> I think this could be done in smaller bites. At least the
>> MIPS_{PYHS,KSEGx}_TO_{KSEGx,PHYS} stuff can be done as a separate
>> patch.
[...]
> Thanks for the review, I'll try to get the patches other than pmap-n64
> in first (with mentor approval). I'll post a new split version of
> pmap-n64 after that.
Here are the pmap changes again, along with a ddb patch.
kseg-def-to-cpu.h.patch
Move KSEG address definitions from cpu.h to cpuregs.h with the other
definitions, add some XKPHYS related definitions.
mips-pmap-intial-n64.patch (from Juli's branch)
Initial changes to pmap.c for n64 support. When compiled for n64, pmap
can use XKPHYS for a lot of its operations. The page tables are still
2-level.
mips-tlb64.patch (from Juli's branch)
64 bit TLB definitions.
mips-ddb-64.patch (from Juli's branch)
Minor fixups for ddb support.
This should get n64 up to mountroot - let me know you comments.
Thanks,
JC.
[-- Attachment #2 --]
Index: sys/mips/include/cpuregs.h
===================================================================
--- sys/mips/include/cpuregs.h (revision 209756)
+++ sys/mips/include/cpuregs.h (working copy)
@@ -78,6 +78,9 @@
* Caching of mapped addresses is controlled by bits in the TLB entry.
*/
+#define MIPS_KSEG0_LARGEST_PHYS (0x20000000)
+#define MIPS_PHYS_MASK (0x1fffffff)
+
#if !defined(_LOCORE)
#define MIPS_KUSEG_START 0x00000000
#define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000)
@@ -91,8 +94,19 @@
#define MIPS_KSEG2_START MIPS_KSSEG_START
#define MIPS_KSEG2_END MIPS_KSSEG_END
-#endif
+#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START)
+#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START)
+#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
+#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
+
+#define MIPS_IS_KSEG0_ADDR(x) \
+ (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \
+ ((vm_offset_t)(x) <= MIPS_KSEG0_END))
+#define MIPS_IS_KSEG1_ADDR(x) \
+ (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \
+ ((vm_offset_t)(x) <= MIPS_KSEG1_END))
+
#define MIPS_XKPHYS_START 0x8000000000000000
#define MIPS_XKPHYS_END 0xbfffffffffffffff
@@ -101,14 +115,21 @@
#define MIPS_PHYS_TO_XKPHYS(cca,x) \
((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
-#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x07ffffffffffffffULL)
+#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
+ ((0x2ULL << 62) | ((unsigned long long)(MIPS_XKPHYS_CCA_CNC) << 59) | (x))
+#define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
+ ((0x2ULL << 62) | ((unsigned long long)(MIPS_XKPHYS_CCA_UC) << 59) | (x))
+#define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x07ffffffffffffffULL)
+
#define MIPS_XUSEG_START 0x0000000000000000
#define MIPS_XUSEG_END 0x0000010000000000
#define MIPS_XKSEG_START 0xc000000000000000
#define MIPS_XKSEG_END 0xc00000ff80000000
+#endif
+
/* CPU dependent mtc0 hazard hook */
#ifdef TARGET_OCTEON
#define COP0_SYNC nop; nop; nop; nop; nop;
Index: sys/mips/include/cpu.h
===================================================================
--- sys/mips/include/cpu.h (revision 209756)
+++ sys/mips/include/cpu.h (working copy)
@@ -49,23 +49,6 @@
#include <machine/endian.h>
-#define MIPS_KSEG0_LARGEST_PHYS (0x20000000)
-#define MIPS_PHYS_MASK (0x1fffffff)
-
-#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START)
-#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START)
-#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
-#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
-
-#define MIPS_IS_KSEG0_ADDR(x) \
- (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \
- ((vm_offset_t)(x) <= MIPS_KSEG0_END))
-#define MIPS_IS_KSEG1_ADDR(x) \
- (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \
- ((vm_offset_t)(x) <= MIPS_KSEG1_END))
-#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \
- MIPS_IS_KSEG1_ADDR(x))
-
/*
* Status register.
*/
[-- Attachment #3 --]
Index: sys/mips/mips/pmap.c
===================================================================
--- sys/mips/mips/pmap.c (revision 209756)
+++ sys/mips/mips/pmap.c (working copy)
@@ -128,7 +128,11 @@
#define pmap_segshift(v) (((v) >> SEGSHIFT) & (NPDEPG - 1))
#define segtab_pde(m, v) ((m)[pmap_segshift((v))])
+#if defined(__mips_n64)
+#define NUSERPGTBLS (NPDEPG)
+#else
#define NUSERPGTBLS (pmap_segshift(VM_MAXUSER_ADDRESS))
+#endif
#define mips_segtrunc(va) ((va) & ~SEGOFSET)
#define is_kernel_pmap(x) ((x) == kernel_pmap)
@@ -310,7 +310,7 @@
}
/*
- * Bootstrap the system enough to run with virtual memory. This
+ * Bootstrap the system enough to run with virtual memory. This
* assumes that the phys_avail array has been initialized.
*/
void
@@ -330,14 +330,11 @@
phys_avail[i] = round_page(phys_avail[i]);
phys_avail[i + 1] = trunc_page(phys_avail[i + 1]);
- if (phys_avail[i + 1] >= MIPS_KSEG0_LARGEST_PHYS)
- memory_larger_than_512meg++;
if (i < 2)
continue;
if (phys_avail[i - 2] > phys_avail[i]) {
vm_paddr_t ptemp[2];
-
ptemp[0] = phys_avail[i + 0];
ptemp[1] = phys_avail[i + 1];
@@ -350,6 +347,11 @@
}
}
+#if !defined(__mips_n64)
+ if (phys_avail[i - 1] >= MIPS_KSEG0_LARGEST_PHYS)
+ memory_larger_than_512meg = 1;
+#endif
+
/*
* Copy the phys_avail[] array before we start stealing memory from it.
*/
@@ -384,7 +386,6 @@
*/
kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT);
-
virtual_avail = VM_MIN_KERNEL_ADDRESS;
virtual_end = VM_MAX_KERNEL_ADDRESS;
@@ -758,11 +759,21 @@
* update '*virt' with the first usable address after the mapped
* region.
*/
+#if defined(__mips_n64)
vm_offset_t
pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
{
+ return (MIPS_PHYS_TO_XKPHYS_CACHED(start));
+}
+#else
+vm_offset_t
+pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot)
+{
vm_offset_t va, sva;
+ if (end <= MIPS_KSEG0_LARGEST_PHYS)
+ return (MIPS_PHYS_TO_KSEG0(start));
+
va = sva = *virt;
while (start < end) {
pmap_kenter(va, start);
@@ -772,6 +783,7 @@
*virt = va;
return (sva);
}
+#endif
/*
* Add a list of wired pages to the kva
@@ -2027,9 +2039,20 @@
* Make a temporary mapping for a physical address. This is only intended
* to be used for panic dumps.
*/
+#if defined(__mips_n64)
void *
pmap_kenter_temporary(vm_paddr_t pa, int i)
{
+ return ((void *)MIPS_PHYS_TO_XKPHYS_CACHED(pa));
+}
+void
+pmap_kenter_temporary_free(vm_paddr_t pa)
+{
+}
+#else
+void *
+pmap_kenter_temporary(vm_paddr_t pa, int i)
+{
vm_offset_t va;
register_t intr;
if (i != 0)
@@ -2087,6 +2110,7 @@
sysm->valid1 = 0;
}
}
+#endif
/*
* Moved the code to Machine Independent
@@ -2193,11 +2217,23 @@
* pmap_zero_page zeros the specified hardware page by mapping
* the page into KVM and using bzero to clear its contents.
*/
+#if defined (__mips_n64)
void
pmap_zero_page(vm_page_t m)
{
vm_offset_t va;
vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
+
+ va = MIPS_PHYS_TO_XKPHYS_CACHED(phys);
+ bzero((caddr_t)va, PAGE_SIZE);
+ mips_dcache_wbinv_range(va, PAGE_SIZE);
+}
+#else
+void
+pmap_zero_page(vm_page_t m)
+{
+ vm_offset_t va;
+ vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
register_t intr;
if (phys < MIPS_KSEG0_LARGEST_PHYS) {
@@ -2214,18 +2250,30 @@
PMAP_LMEM_UNMAP();
}
}
-
+#endif
/*
* pmap_zero_page_area zeros the specified hardware page by mapping
* the page into KVM and using bzero to clear its contents.
*
* off and size may not cover an area beyond a single hardware page.
*/
+#if defined (__mips_n64)
void
pmap_zero_page_area(vm_page_t m, int off, int size)
{
vm_offset_t va;
vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
+
+ va = MIPS_PHYS_TO_XKPHYS_CACHED(phys);
+ bzero((char *)(caddr_t)va + off, size);
+ mips_dcache_wbinv_range(va + off, size);
+}
+#else
+void
+pmap_zero_page_area(vm_page_t m, int off, int size)
+{
+ vm_offset_t va;
+ vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
register_t intr;
if (phys < MIPS_KSEG0_LARGEST_PHYS) {
@@ -2241,12 +2289,25 @@
PMAP_LMEM_UNMAP();
}
}
+#endif
+#if defined (__mips_n64)
void
pmap_zero_page_idle(vm_page_t m)
{
vm_offset_t va;
vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
+
+ va = MIPS_PHYS_TO_XKPHYS_CACHED(phys);
+ bzero((caddr_t)va, PAGE_SIZE);
+ mips_dcache_wbinv_range(va, PAGE_SIZE);
+}
+#else
+void
+pmap_zero_page_idle(vm_page_t m)
+{
+ vm_offset_t va;
+ vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
register_t intr;
if (phys < MIPS_KSEG0_LARGEST_PHYS) {
@@ -2262,6 +2323,7 @@
PMAP_LMEM_UNMAP();
}
}
+#endif
/*
* pmap_copy_page copies the specified (machine independent)
@@ -2269,12 +2331,28 @@
* bcopy to copy the page, one machine dependent page at a
* time.
*/
+#if defined (__mips_n64)
void
pmap_copy_page(vm_page_t src, vm_page_t dst)
{
vm_offset_t va_src, va_dst;
vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src);
vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst);
+
+ pmap_flush_pvcache(src);
+ mips_dcache_wbinv_range_index(MIPS_PHYS_TO_XKPHYS_CACHED(phy_dst), PAGE_SIZE);
+ va_src = MIPS_PHYS_TO_XKPHYS_CACHED(phy_src);
+ va_dst = MIPS_PHYS_TO_XKPHYS_CACHED(phy_dst);
+ bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
+ mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
+}
+#else
+void
+pmap_copy_page(vm_page_t src, vm_page_t dst)
+{
+ vm_offset_t va_src, va_dst;
+ vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src);
+ vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst);
register_t intr;
if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) {
@@ -2299,6 +2377,7 @@
PMAP_LMEM_UNMAP();
}
}
+#endif
/*
* Returns true if the pmap's pv is one of the first
@@ -2705,9 +2784,21 @@
* routine is intended to be used for mapping device memory,
* NOT real memory.
*/
+#if defined(__mips_n64)
void *
pmap_mapdev(vm_offset_t pa, vm_size_t size)
{
+ return ((void *)MIPS_PHYS_TO_XKPHYS_UNCACHED(pa));
+}
+
+void
+pmap_unmapdev(vm_offset_t va, vm_size_t size)
+{
+}
+#else
+void *
+pmap_mapdev(vm_offset_t pa, vm_size_t size)
+{
vm_offset_t va, tmpva, offset;
/*
@@ -2751,6 +2842,7 @@
pmap_kremove(tmpva);
kmem_free(kernel_map, base, size);
}
+#endif
/*
* perform the pmap work for mincore
@@ -3067,6 +3159,7 @@
PHYS_TO_VM_PAGE(pa)->md.pv_flags |= (PV_TABLE_REF | PV_TABLE_MOD);
}
+
/*
* Routine: pmap_kextract
* Function:
@@ -3076,41 +3169,68 @@
/* PMAP_INLINE */ vm_offset_t
pmap_kextract(vm_offset_t va)
{
- vm_offset_t pa = 0;
+ int mapped;
- if (va < MIPS_KSEG0_START) {
- /* user virtual address */
+ /*
+ * First, the direct-mapped regions.
+ */
+#if defined(__mips_n64)
+ if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END)
+ return (MIPS_XKPHYS_TO_PHYS(va));
+#endif
+
+ if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END)
+ return (MIPS_KSEG0_TO_PHYS(va));
+
+ if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END)
+ return (MIPS_KSEG1_TO_PHYS(va));
+
+ /*
+ * User virtual addresses.
+ */
+ if (va < VM_MAXUSER_ADDRESS) {
pt_entry_t *ptep;
if (curproc && curproc->p_vmspace) {
ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va);
- if (ptep)
- pa = TLBLO_PTE_TO_PA(*ptep) |
- (va & PAGE_MASK);
+ if (ptep) {
+ return (TLBLO_PTE_TO_PA(*ptep) |
+ (va & PAGE_MASK));
+ }
+ return (0);
}
- } else if (va >= MIPS_KSEG0_START &&
- va < MIPS_KSEG1_START)
- pa = MIPS_KSEG0_TO_PHYS(va);
- else if (va >= MIPS_KSEG1_START &&
- va < MIPS_KSEG2_START)
- pa = MIPS_KSEG1_TO_PHYS(va);
- else if (va >= MIPS_KSEG2_START && va < VM_MAX_KERNEL_ADDRESS) {
+ }
+
+ /*
+ * Should be kernel virtual here, otherwise fail
+ */
+ mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END);
+#if defined(__mips_n64)
+ mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END);
+#endif
+ /*
+ * Kernel virtual.
+ */
+
+ if (mapped) {
pt_entry_t *ptep;
/* Is the kernel pmap initialized? */
if (kernel_pmap->pm_active) {
- /* Its inside the virtual address range */
+ /* It's inside the virtual address range */
ptep = pmap_pte(kernel_pmap, va);
if (ptep) {
return (TLBLO_PTE_TO_PA(*ptep) |
(va & PAGE_MASK));
}
- return (0);
}
+ return (0);
}
- return pa;
+
+ panic("%s for unknown address space %p.", __func__, (void *)va);
}
+
void
pmap_flush_pvcache(vm_page_t m)
{
[-- Attachment #4 --]
Index: sys/mips/include/pte.h
===================================================================
--- sys/mips/include/pte.h (revision 209756)
+++ sys/mips/include/pte.h (working copy)
@@ -73,8 +73,24 @@
* Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page.
*/
#define TLBHI_ASID_MASK (0xff)
+#if defined(__mips_n64)
+#define TLBHI_R_SHIFT 62
+#define TLBHI_R_USER (0x00UL << TLBHI_R_SHIFT)
+#define TLBHI_R_SUPERVISOR (0x01UL << TLBHI_R_SHIFT)
+#define TLBHI_R_KERNEL (0x03UL << TLBHI_R_SHIFT)
+#define TLBHI_R_MASK (0x03UL << TLBHI_R_SHIFT)
+#define TLBHI_VA_R(va) ((va) & TLBHI_R_MASK)
+#define TLBHI_FILL_SHIFT 40
+#define TLBHI_VPN2_SHIFT (TLB_PAGE_SHIFT + 1)
+#define TLBHI_VPN2_MASK (((~((1UL << TLBHI_VPN2_SHIFT) - 1)) << (63 - TLBHI_FILL_SHIFT)) >> (63 - TLBHI_FILL_SHIFT))
+#define TLBHI_VA_TO_VPN2(va) ((va) & TLBHI_VPN2_MASK)
+#define TLBHI_ENTRY(va, asid) ((TLBHI_VA_R((va))) /* Region. */ | \
+ (TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \
+ ((asid) & TLBHI_ASID_MASK))
+#else
#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1)
#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
+#endif
#ifndef _LOCORE
typedef uint32_t pt_entry_t;
[-- Attachment #5 --]
Index: sys/mips/mips/db_interface.c
===================================================================
--- sys/mips/mips/db_interface.c (revision 209521)
+++ sys/mips/mips/db_interface.c (working copy)
@@ -115,12 +115,12 @@
static int
db_frame(struct db_variable *vp, db_expr_t *valuep, int op)
{
- int *reg;
+ register_t *reg;
if (kdb_frame == NULL)
return (0);
- reg = (int *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep);
+ reg = (register_t *)((uintptr_t)kdb_frame + (size_t)(intptr_t)vp->valuep);
if (op == DB_VAR_GET)
*valuep = *reg;
else
Index: sys/mips/mips/db_trace.c
===================================================================
--- sys/mips/mips/db_trace.c (revision 209521)
+++ sys/mips/mips/db_trace.c (working copy)
@@ -140,7 +140,7 @@
}
/* check for bad SP: could foul up next frame */
/*XXX MIPS64 bad: this hard-coded SP is lame */
- if (sp & 3 || sp < 0x80000000) {
+ if (sp & 3 || (uintptr_t)sp < 0x80000000u) {
(*printfn) ("SP 0x%x: not in kernel\n", sp);
ra = 0;
subr = 0;
@@ -269,27 +269,27 @@
mask |= (1 << i.IType.rt);
switch (i.IType.rt) {
case 4:/* a0 */
- args[0] = kdbpeek((int *)(sp + (short)i.IType.imm));
+ args[0] = kdbpeek((int *)((intptr_t)sp + (short)i.IType.imm));
valid_args[0] = 1;
break;
case 5:/* a1 */
- args[1] = kdbpeek((int *)(sp + (short)i.IType.imm));
+ args[1] = kdbpeek((int *)((intptr_t)sp + (short)i.IType.imm));
valid_args[1] = 1;
break;
case 6:/* a2 */
- args[2] = kdbpeek((int *)(sp + (short)i.IType.imm));
+ args[2] = kdbpeek((int *)((intptr_t)sp + (short)i.IType.imm));
valid_args[2] = 1;
break;
case 7:/* a3 */
- args[3] = kdbpeek((int *)(sp + (short)i.IType.imm));
+ args[3] = kdbpeek((int *)((intptr_t)sp + (short)i.IType.imm));
valid_args[3] = 1;
break;
case 31: /* ra */
- ra = kdbpeek((int *)(sp + (short)i.IType.imm));
+ ra = kdbpeek((int *)((intptr_t)sp + (short)i.IType.imm));
}
break;
@@ -303,27 +303,27 @@
mask |= (1 << i.IType.rt);
switch (i.IType.rt) {
case 4:/* a0 */
- args[0] = kdbpeekD((int *)(sp + (short)i.IType.imm));
+ args[0] = kdbpeekD((int *)((intptr_t)sp + (short)i.IType.imm));
valid_args[0] = 1;
break;
case 5:/* a1 */
- args[1] = kdbpeekD((int *)(sp + (short)i.IType.imm));
+ args[1] = kdbpeekD((int *)((intptr_t)sp + (short)i.IType.imm));
valid_args[1] = 1;
break;
case 6:/* a2 */
- args[2] = kdbpeekD((int *)(sp + (short)i.IType.imm));
+ args[2] = kdbpeekD((int *)((intptr_t)sp + (short)i.IType.imm));
valid_args[2] = 1;
break;
case 7:/* a3 */
- args[3] = kdbpeekD((int *)(sp + (short)i.IType.imm));
+ args[3] = kdbpeekD((int *)((intptr_t)sp + (short)i.IType.imm));
valid_args[3] = 1;
break;
case 31: /* ra */
- ra = kdbpeekD((int *)(sp + (short)i.IType.imm));
+ ra = kdbpeekD((int *)((intptr_t)sp + (short)i.IType.imm));
}
break;
@@ -369,7 +369,7 @@
int
-db_md_set_watchpoint(db_expr_t addr, db_expr_t size)
+db_md_set_watchpoint(intptr_t addr, db_expr_t size)
{
return(0);
@@ -377,7 +377,7 @@
int
-db_md_clr_watchpoint( db_expr_t addr, db_expr_t size)
+db_md_clr_watchpoint(intptr_t addr, db_expr_t size)
{
return(0);
@@ -403,8 +403,8 @@
struct pcb *ctx;
if (thr == curthread) {
- sp = (register_t)__builtin_frame_address(0);
- ra = (register_t)__builtin_return_address(0);
+ sp = (register_t)(intptr_t)__builtin_frame_address(0);
+ ra = (register_t)(intptr_t)__builtin_return_address(0);
__asm __volatile(
"jal 99f\n"
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?AANLkTik8fBlxMyZ3AZETF_7DvlSpPsx2hozIWinRy0U0>