Date: Tue, 4 Oct 2011 13:49:13 -0400 From: Andrew Duane <aduane@juniper.net> To: Jayachandran C. <jchandra@freebsd.org> Cc: Alexander Motin <mav@freebsd.org>, Kostik, "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org>, Belousov <kostikbel@gmail.com> Subject: RE: svn commit: r225892 - head/sys/mips/mips Message-ID: <AC6674AB7BC78549BB231821ABF7A9AEB80CB20079@EMBX01-WF.jnpr.net> In-Reply-To: <CA%2B7sy7AncTdRDN88DaiPsBDc=PQ3N6UR9VAb7chOOp7XDXS=Sw@mail.gmail.com> References: <kor1ebmmdclae4u7bstwrc2c.1317741744919@email.android.com> <AC6674AB7BC78549BB231821ABF7A9AEB80CB1FE93@EMBX01-WF.jnpr.net> <CA%2B7sy7AncTdRDN88DaiPsBDc=PQ3N6UR9VAb7chOOp7XDXS=Sw@mail.gmail.com>
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An assert, or some other check would work. Could you just add "EndWaitSkip = - StartWaitSkip" somehow? I just worry that some day it won't be 16 bytes a= ny more.... =A0................................... Andrew Duane Juniper Networks o=A0=A0=A0+1 978 589 0551 m=A0 +1 603-770-7088 aduane@juniper.net =A0 > -----Original Message----- > From: c.jayachandran@gmail.com [mailto:c.jayachandran@gmail.com] On > Behalf Of Jayachandran C. > Sent: Tuesday, October 04, 2011 10:48 AM > To: Andrew Duane > Cc: Warner Losh; Adrian Chadd; Kostik Belousov; Alexander Motin; > freebsd-mips@freebsd.org > Subject: Re: svn commit: r225892 - head/sys/mips/mips >=20 > On Tue, Oct 4, 2011 at 9:34 PM, Andrew Duane <aduane@juniper.net> > wrote: > > The MIPS manual volume 3 says there is a 3 cycle "typical" wait > between an MTC0 that messes with Status[IE] and an interrupted > instruction. That hazard doesn't seem to apply here, to any of the > cases we have. > > > > I do have a question: in StartWaitSkip, the value of Status[IE] is > being toggled, not cleared. Is that correct? Do we always guarantee > that it will be set on entry here? >=20 > Interrupts have to be enabled in cpu_idle(), there is an assert in the > beginning of cpu_idle which checks this. >=20 > > I had also made a comment about the "PTR_ADDU k1, 16 =A0 =A0# skip over > wait" in MipsKernIntr; I think it would be safer (and clearer) to do > "PTR_LA =A0 =A0 =A0 =A0k1, EndWaitSkip" instead. >=20 > Loading an immediate address takes more instructions (esp in 64 bit) > adding 16 is just one instruction. I should really add an KASSERT > somewhere to make sure that EndWaitSkip - StartWaitSkip is 16... >=20 > JC.
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