Date: Wed, 5 Nov 1997 10:58:39 -0500 (EST) From: Chuck Robey <chuckr@glue.umd.edu> To: Bob K <melange@europa.humberc.on.ca> Cc: freebsd-current@FreeBSD.ORG Subject: Re: memory out of range??? Message-ID: <Pine.BSF.3.96.971105105000.3678A-100000@localhost> In-Reply-To: <Pine.BSF.3.96.971105064301.1203E-100000@europa.humberc.on.ca>
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On Wed, 5 Nov 1997, Bob K wrote: > On Wed, 5 Nov 1997, Mike Smith wrote: > > > > > > > One minor problem (not related to the bounce problem): P-II processors > > > don't cache above 512MB. > > > > Is this addressed by the (rumoured?) PII's with 1024K caches? > > I could be wrong about this, but I thought that the amount of memory that > is cachable is dependant upon the chipset that the motherboard is using, > rather than the processor itself. Or is this different now that the L2 > cache is located in the chip (cartridge)? The Pentiums cache off the main chip, so the chipset gets into the loop. The Pentium Pros cache inside the chip, so the chipset doesn't get involved. Actually, the Pentium Pros _do_ go off-chip, but the chip is inside the limits of the IC package, it doesn't go to a separate memory array. This means the access of cache memory is faster. One the Pentiums, it's at bus speed, on the PPros, it's at processor speed. To illustrate, my Pentium 166 has a bus speed of 66 MHz, and that's the speed it accesses cache at. The PPro I have is a 166 also, and accesses cache at 166 MHz, not 66 MHz, which is quite a speedup. You can't upgrade the cache without swapping out the CPU, tho, on the PPros. > > > ----------------------------+----------------------------------------------- Chuck Robey | Interests include any kind of voice or data chuckr@glue.umd.edu | communications topic, C programming, and Unix. 213 Lakeside Drive Apt T-1 | Greenbelt, MD 20770 | I run Journey2 and picnic, both FreeBSD (301) 220-2114 | version 3.0 current -- and great FUN! ----------------------------+-----------------------------------------------
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