Date: Fri, 18 Nov 2022 05:30:59 +0000 From: "Chen, Alvin W" <Weike.Chen@Dell.com> To: Konstantin Belousov <kostikbel@gmail.com> Cc: Amar Takhar <verm@darkbeer.org>, "freebsd-current@freebsd.org" <freebsd-current@freebsd.org> Subject: RE: Status of Intel Hybrid CPU support (Alder Lake/Raptor Lake) support Message-ID: <PH0PR19MB49381A82EA63FB02288C14289E099@PH0PR19MB4938.namprd19.prod.outlook.com> In-Reply-To: <Y3R08CWLZT0uMQs5@kib.kiev.ua> References: <PH0PR19MB49386F16177AC787CFFAD05C9E339@PH0PR19MB4938.namprd19.prod.outlook.com> <CB6714BB-F070-436A-9324-1053648A7DE6@karels.net> <PH0PR19MB4938527239BDA1AA6FFE5C129E059@PH0PR19MB4938.namprd19.prod.outlook.com> <Y3HppLvsWTqqGNoO@kib.kiev.ua> <20221114174812.GA20495@darkbeer.org> <PH0PR19MB49388444FDBEB729A0F286019E049@PH0PR19MB4938.namprd19.prod.outlook.com> <Y3R08CWLZT0uMQs5@kib.kiev.ua>
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> > I am not familiar with TLB part implementation for BSD. Based on your > patch, it looks like disable PCID or force flush TLB for E core. Is that = right? > > Would you mind explain a little more to help understand the code? >=20 > The patch does what its title said. On small cores it does not rely on IN= VLPG > to flush global TLB entries. Instead, total flush of TLB with INVPCID > instruction is performed. >=20 > For large cores, no change in behavior is intended. Thanks. I apply the patch and test for 10 hours+ on my ADL-P laptop. It wor= ks well, and the issue is never reproduced. Internal Use - Confidential
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