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Date:      Mon, 26 Oct 2009 12:31:12 -0700
From:      Sean Bruno <sean.bruno@dsl-only.net>
To:        Fabio <info@maconnect.ch>
Cc:        freebsd-firewire <freebsd-firewire@freebsd.org>
Subject:   [Fwd: Re: firewire issue]
Message-ID:  <1256585472.2607.4.camel@Lappy>

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[-- Attachment #1 --]
Look over this patch from Andreas.  I haven't done anything with it as I
don't have the h/w to test with.

Sean

[-- Attachment #2 --]
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Date: Mon, 25 May 2009 23:12:25 +0200
From: Andreas Tobler <andreast-list@fgznet.ch>
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To: Sean Bruno <sean.bruno@dsl-only.net>
Subject: Re: firewire issue
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Sean Bruno wrote:
> On Mon, 2009-05-25 at 22:30 +0200, Andreas Tobler wrote:
>> Sean Bruno wrote:
>>> On Mon, 2009-05-25 at 21:59 +0200, Andreas Tobler wrote:
>>>> Sean Bruno wrote:
>>>>> On Sun, 2009-05-24 at 22:57 +0200, Andreas Tobler wrote:
>>>>>> Sean Bruno wrote:
>>>>>>> On Sat, 2009-05-23 at 22:48 +0200, Andreas Tobler wrote:
>>>>>>>> Sean Bruno wrote:
>>>>>>>>> On Tue, 2009-05-19 at 06:49 +0200, Andreas Tobler wrote:
>>>>>>>>>> Sean Bruno wrote:
>>>>>>>>>>> Hey ... do you have the IEEE firewire specifications?
>>>>>>>>>>>
>>>>>>>>>>> I have them if you would like a copy.
>>>>>>>>>> Yes, please.
>>>>>>>>>>
>>>>>>>>>> Andreas
>>>>>>>>> http://consultcsg.com/firewire.tar.gz
>>>>>>>>>
>>>>>>>>> Everything I have.  
>>>>>>>> Thank you!
>>>>>>>>
>>>>>>>> The docs confirmed that it is not a protocol issue.
>>>>>>>> Here I fight with silicon, I need to find out why the bus reset doesn't 
>>>>>>>> behave as expected.
>>>>>>>> My current mods let me discover the attached fw disk. Unfortunately a 
>>>>>>>> bus reset kills further operation.
>>>>>>>>
>>>>>>>> So I have to investigate in this direction...
>>>>>>>>
>>>>>>>> Anyway, thanks again for the standards.
>>>>>>>>
>>>>>>>> Regards,
>>>>>>>> Andreas
>>>>>>> I would *assume* that linux had dealt with this.  However, I don't see
>>>>>>> any other FreeBSD users complaining about their G3's ... Is this problem
>>>>>>> specific to the Mac that you have, or is affecting all of the G3's?
>>>>>> I don't know if Linux finally dealt with this issue. I asked the fw guy 
>>>>>> on the Linux side and he couldn't confirm if the issue is solved. I need 
>>>>>> to ask BenH, the chief crack.
>>>>>>
>>>>>> It only affects the machines with
>>>>>> #define		FW_DEVICE_UNINORTH_V1	(0x0018 << 16)
>>>>>> and
>>>>>> #define		FW_VENDORID_APPLE	0x106b
>>>>>>
>>>>>> It is an old machine, but this hardware really rocks under *BSD iso. Darwin.
>>>>>>
>>>>>> And true, it is not lifetime critical :)
>>>>>>
>>>>>>
>>>>>> It is more a prove of concept.
>>>>>>
>>>>>> Andreas
>>>>> Interesting.  Ask the freebsd-hackers list if anyone can reproduce the
>>>>> issue on the same hardware.
>>>> hehe, I doubt, but it might be chance.
>>>>
>>>> Btw, I noticed a panic when trying my mods with your latest patch you 
>>>> sent me, the one for sparc64.
>>>> My mods are only related to byteswapping of packets. And there is no 
>>>> device attached.
>>>>
>>>> I have to type the panic by hand:
>>>>
>>>> fwohci0: initiate bus reset
>>>> fwohci0: fwphy_rddata:: 0x1, retry=6
>>>> Sleeping thread (tid 100069, pid 840) owns a non-sleepable lock
>>>> mi_switch
>>>> sleepq_switch
>>>> sleepq_timedwait
>>>> _sleep
>>>> pause
>>>> fwphy_rddata
>>>> fwphy_wrdata
>>>> fwohci_ibr
>>>> firewire_attach
>>>> device_attach
>>>> device_probe_and_attach
>>>> fwohci_pci_add_child
>>>> firewire_identify
>>>> ....
>>>>
>>>> Any blinking leds on your side?
>>>>
>>>> I wonder why fwohci_ibr is coming in that early?
>>>>
>>>> Is this correct?
>>>>
>>>> Andreas
>>>>
>>> Ok, so your modifications without my changes for the card you have in
>>> your sparc64 don't panic?  That would be wierd.
>> Aehm, I meant to say that your patch and my mods produce this panic on 
>> the iMac. The sparc64 is in sleep mode until I get the second cpu. And I 
>> doubt that my mods will panic the sparc64.
>>
>> I tested my mods against a newer PowerBook and an i386 and I took care 
>> that I do not break existing functionalitiy. Also, my mods are towards 
>> current svn. I only wondered if your patch might help here in my imac case.
>>
>>> Also, can you send me the pciconf -lv for the sparc64 board that I
>>> changed the code for?
>> I will, but as said, currently it is shutdown.
>>
>> Andreas
> 
> 
> Ah.  Ok, please send me your current diff and I'll look at it.

Attached, I'm not happy with, but it is wip.

The mod in the firewire.c where I don't set the max_nod to -1 is 
necessary to prohibit an infinite loop. The BusReset sets the max_node 
to -1 and currently I can't set it to a meaningful value.

Below the messages w/o debug. the "< ------ this one" bothers me.
There is one disk attached. firewire and sbp loaded via kldload.
So far it looks correct to me except the bus resets?

Andreas

May 25 23:02:04 imacb kernel: fwohci0: <Apple UniNorth, v1> mem 
0xf5000000-0xf5000fff irq 40 at device 14.0 on pci2
May 25 23:02:04 imacb kernel: fwohci0: [ITHREAD]
May 25 23:02:04 imacb kernel: fwohci0: Uninorth v1
May 25 23:02:04 imacb kernel: fwohci0: OHCI version 1.0 (ROM=0)
May 25 23:02:04 imacb kernel: fwohci0: No. of Isochronous channels is 4.
May 25 23:02:04 imacb kernel: fwohci0: EUI64 00:30:65:ff:fe:aa:7c:d0
May 25 23:02:04 imacb kernel: fwohci0: Phy 1394a available S400, 2 ports.
May 25 23:02:04 imacb kernel: fwohci0: Link S400, max_rec 2048 bytes.
May 25 23:02:04 imacb kernel: firewire0: <IEEE1394(FireWire) bus> on fwohci0
May 25 23:02:04 imacb kernel: fwohci0: Initiate bus reset
May 25 23:02:04 imacb kernel: fwohci0: fwohci_intr_core: BUS reset 
status: 0xffffffff
May 25 23:02:04 imacb kernel: fwohci0: fwohci_intr_core: enable bus 
reset interrupt
May 25 23:02:04 imacb kernel: fwohci0: fwohci_intr_core: 
node_id=0x00000001, SelfID Count=1, CYCLEMASTER mode
May 25 23:02:04 imacb kernel: firewire0: 2 nodes, maxhop <= 1 cable IRM 
irm(1)  (me)
May 25 23:02:04 imacb kernel: firewire0: bus manager 1
May 25 23:02:04 imacb kernel: fwohci0: fwohci_intr_core: BUS reset 
status: 0x6 < ------ this one
May 25 23:02:04 imacb kernel: fwohci0: txd err= 3 miss Ack err
May 25 23:02:05 imacb kernel: fwohci0: fwohci_intr_core: BUS reset 
status: 0x5 < ------ this one
May 25 23:02:05 imacb kernel: firewire0: fw_explore_node: Pre 1394a-2000 
detected
May 25 23:02:05 imacb kernel: firewire0: New S400 device ID:0050770e00002fd8
May 25 23:02:13 imacb kernel: sbp0: <SBP-2/SCSI over FireWire> on firewire0
May 25 23:02:13 imacb kernel: sbp0: sbp_show_sdev_info: sbp0:0:0: 
ordered:1 type:14 EUI:0050770e00002fd8 node:0 speed:2 maxrec:8
May 25 23:02:13 imacb kernel: sbp0: sbp_show_sdev_info: sbp0:0:0 
'Prolific PL3507 Combo Device' '(1394 ATAPI,Rev 1.00)' '012804'
May 25 23:02:14 imacb kernel: fwohci0: fwohci_intr_core: BUS reset 
status: 0x7 < ---- this one

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Index: fwohci_pci.c
===================================================================
--- fwohci_pci.c	(revision 192695)
+++ fwohci_pci.c	(working copy)
@@ -196,6 +196,10 @@
 		device_set_desc(dev, "Apple UniNorth");
 		return BUS_PROBE_DEFAULT;
 	}
+	if (id == (FW_VENDORID_APPLE | FW_DEVICE_UNINORTH_V1)) {
+		device_set_desc(dev, "Apple UniNorth, v1");
+		return BUS_PROBE_DEFAULT;
+	}
 	if (id == (FW_VENDORID_LUCENT | FW_DEVICE_FW322)) {
 		device_set_desc(dev, "Lucent FW322/323");
 		return BUS_PROBE_DEFAULT;
@@ -285,6 +289,10 @@
 	fwohci_softc_t *sc = device_get_softc(self);
 	int err;
 	int rid;
+	uint32_t id;
+	
+	sc->old_uninorth = 0;
+
 #if defined(__DragonFly__) || __FreeBSD_version < 500000
 	int intr;
 	/* For the moment, put in a message stating what is wrong */
@@ -383,6 +391,12 @@
 			return (ENOMEM);
 	}
 
+	id = pci_get_devid(self);
+	if (id == (FW_VENDORID_APPLE | FW_DEVICE_UNINORTH_V1)) {
+	        sc->old_uninorth = 1;
+		device_printf(self, "Uninorth v1\n");
+	}
+
 	err = fwohci_init(sc, self);
 
 	if (err) {
Index: firewire.c
===================================================================
--- firewire.c	(revision 192695)
+++ firewire.c	(working copy)
@@ -77,7 +77,7 @@
 	struct crom_chunk hw;
 };
 
-int firewire_debug=0, try_bmr=1, hold_count=0;
+int firewire_debug=2, try_bmr=1, hold_count=0;
 SYSCTL_INT(_debug, OID_AUTO, firewire_debug, CTLFLAG_RW, &firewire_debug, 0,
 	"FireWire driver debug flag");
 SYSCTL_NODE(_hw, OID_AUTO, firewire, CTLFLAG_RD, 0, "FireWire Subsystem");
@@ -632,7 +632,7 @@
 	CSRARC(fc, TOPO_MAP + 8) = 0;
 	fc->irm = -1;
 
-	fc->max_node = -1;
+	/*fc->max_node = -1; */
 
 	for(i = 2; i < 0x100/4 - 2 ; i++){
 		CSRARC(fc, SPED_MAP + i * 4) = 0;
Index: fwohci.c
===================================================================
--- fwohci.c	(revision 192695)
+++ fwohci.c	(working copy)
@@ -79,6 +79,7 @@
 #undef OHCI_DEBUG
 
 static int nocyclemaster = 0;
+static int old_uninorth = 0;
 int firewire_phydma_enable = 1;
 SYSCTL_DECL(_hw_firewire);
 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0,
@@ -266,6 +267,15 @@
 
 d_ioctl_t fwohci_ioctl;
 
+#if BYTE_ORDER == BIG_ENDIAN
+#define FWOHCI_DMA_READ_UNI(x)			\
+  old_uninorth ? (x) : FWOHCI_DMA_READ(x)
+#define FWOHCI_DMA_WRITE_UNI(x,y)			\
+  old_uninorth ? ((x) = (y)) : FWOHCI_DMA_WRITE(x,y)
+#else
+#define FWOHCI_DMA_READ_UNI(x) FWOHCI_DMA_READ(x)
+#define FWOHCI_DMA_WRITE_UNI(x,y) FWOHCI_DMA_WRITE(x,y)
+#endif
 /*
  * Communication with PHY device
  */
@@ -624,6 +634,8 @@
 		return (ENXIO);
 	}
 
+	old_uninorth = sc->old_uninorth;
+
 /* Available Isochronous DMA channel probe */
 	OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
 	OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
@@ -952,7 +964,7 @@
 	if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
 		hdr_len = 12;
 	for (i = 0; i < hdr_len/4; i ++)
-		FWOHCI_DMA_WRITE(ld[i], ld[i]);
+	        FWOHCI_DMA_WRITE(ld[i], ld[i]);
 #endif
 
 again:
@@ -1811,7 +1823,7 @@
 fwohci_dump_intr(struct fwohci_softc *sc, uint32_t stat)
 {
 	if(stat & OREAD(sc, FWOHCI_INTMASK))
-		device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
+		device_printf(sc->fc.dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
 			stat & OHCI_INT_EN ? "DMA_EN ":"",
 			stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
 			stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
@@ -1845,11 +1857,13 @@
 
 	FW_GLOCK_ASSERT(fc);
 	if ((stat & OHCI_INT_PHY_BUS_R) && (fc->status != FWBUSRESET)) {
-		fc->status = FWBUSRESET;
+		
 		/* Disable bus reset interrupt until sid recv. */
 		OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_PHY_BUS_R);
 	
-		device_printf(fc->dev, "%s: BUS reset\n", __func__);
+		device_printf(fc->dev, "%s: BUS reset status: 0x%x\n",
+			      __func__, fc->status);
+		fc->status = FWBUSRESET;
 		OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_CYC_LOST);
 		OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
 
@@ -1863,6 +1877,8 @@
 	}
 	if (stat & OHCI_INT_PHY_SID) {
 		/* Enable bus reset interrupt */
+	        device_printf(fc->dev, "%s: enable bus reset interrupt\n",
+			      __func__);
 		OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
 		OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
 
@@ -2037,7 +2053,7 @@
 		return;
 	}
 	for (i = 0; i < plen / 4; i ++)
-		buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
+		buf[i] = FWOHCI_DMA_READ_UNI(sc->sid_buf[i+1]);
 
 	/* pending all pre-bus_reset packets */
 	fwohci_txd(sc, &sc->atrq);
@@ -2076,9 +2092,12 @@
 			"device physically ejected?\n");
 		return (FILTER_STRAY);
 	}
-	if (stat)
-		OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R);
+	
+	if (stat) {
+	        OWRITE(sc, FWOHCI_INTSTATCLR, stat & ~OHCI_INT_PHY_BUS_R);
 
+	}
+
 	stat &= sc->intmask;
 	if (stat == 0)
 		return (FILTER_STRAY);
@@ -2657,7 +2676,7 @@
 	int i;
 #endif
 
-	ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
+	ld0 = FWOHCI_DMA_READ_UNI(fp->mode.ld[0]);
 #if 0
 	printf("ld0: x%08x\n", ld0);
 #endif
@@ -2690,7 +2709,7 @@
 	}
 #if BYTE_ORDER == BIG_ENDIAN
 	for(i = 0; i < slen/4; i ++)
-		fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
+	        fp->mode.ld[i] = FWOHCI_DMA_READ_UNI(fp->mode.ld[i]);
 #endif
 	return(hlen);
 }
@@ -2884,7 +2903,7 @@
 				printf("nvec == 0\n");
 
 /* DMA result-code will be written at the tail of packet */
-			stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer)));
+			stat = FWOHCI_DMA_READ_UNI(*(uint32_t *)(ld - sizeof(struct fwohci_trailer)));
 #if 0
 			printf("plen: %d, stat %x\n",
 			    plen ,stat);
Index: fwohcireg.h
===================================================================
--- fwohcireg.h	(revision 192695)
+++ fwohcireg.h	(working copy)
@@ -73,6 +73,7 @@
 #define		FW_DEVICE_R5C552	(0x0552 << 16)
 #define		FW_DEVICE_PANGEA	(0x0030 << 16)
 #define		FW_DEVICE_UNINORTH	(0x0031 << 16)
+#define		FW_DEVICE_UNINORTH_V1	(0x0018 << 16)
 #define		FW_DEVICE_AIC5800	(0x5800 << 16)
 #define		FW_DEVICE_FW322		(0x5811 << 16)
 #define		FW_DEVICE_7007		(0x7007 << 16)
Index: fwohcivar.h
===================================================================
--- fwohcivar.h	(revision 192695)
+++ fwohcivar.h	(working copy)
@@ -75,6 +75,7 @@
 	struct task fwohci_task_sid;
 	struct task fwohci_task_dma;
 	int cycle_lost;
+        int old_uninorth;
 } fwohci_softc_t;
 
 void fwohci_intr (void *arg);

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