Date: Sat, 8 Apr 1995 12:45:38 -0700 (PDT) From: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> To: phk@ref.tfs.com (Poul-Henning Kamp) Cc: taob@gate.sinica.edu.tw, freebsd-current@FreeBSD.org Subject: Re: Disk performance Message-ID: <199504081945.MAA15893@gndrsh.aac.dev.com> In-Reply-To: <199504081810.LAA22532@ref.tfs.com> from "Poul-Henning Kamp" at Apr 8, 95 11:10:04 am
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> > > Why would taking out the L2 cache slow down data transfer to and > > from the primary cache? > > because checking the L2 takes time, and they don't start the mem-cycle > until they know they missed. You would be right if he was talking about why turning off the L2 cache increases memory speed. But that is not what he said ``taking out L2 cache slowing down L1 cache''. Nothing, nota, zippo, should effect L1 cache speeds other than code changes, and internal clock frequency. Even bus snoops cycles are not suppose to change the L1 cache access since it has a dedicated snoop port (yes, the tags on the internal Pentium cache are multiported, and the data cache is dual ported). Now on the issue you bring up.. seems PC cache designers never heard of implemented pass through memory start cycles with early abort. It's tricky to design, but it elminates the delay due to cache tag lookup and compare time (30nS for most motherboards, 20nS for the new Pipelined Burst stuff). -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Custom computers for FreeBSD
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