Date: Sat, 3 Feb 1996 19:13:06 +1030 (CST) From: Michael Smith <msmith@atrad.adelaide.edu.au> To: jgreco@brasil.moneng.mei.com (Joe Greco) Cc: msmith@atrad.adelaide.edu.au, hackers@freebsd.org Subject: Re: Watchdog timers (was: Re: Multi-Port Async Cards) Message-ID: <199602030843.TAA01018@genesis.atrad.adelaide.edu.au> In-Reply-To: <199602021854.MAA11875@brasil.moneng.mei.com> from "Joe Greco" at Feb 2, 96 12:54:01 pm
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Joe Greco stands accused of saying: > > > If you're going to decode the I/O's already, don't bother with the UART. > > I have a rough schematic for this already, and I'll work on it when I can; > > keep the ideas coming 8) > > Your intent is to emulate the UART? I'm sorry, I'm not THAT good at digital > logic design :-) I wouldn't know where to start. No, not at all! I've been tinkering with various designs, but all of them use a couple of registers and a much more sensible mode of operation. The current leading design has a read/write data register and a command/status register. I've considered having an interrupt generated on any chnage in the status register. All this is a little hypothetical just now, as I'm concentrating on the watchdog card. If it works out, it should do the basics, and with a TXCO on it should give a good, stable frequency reference. Accessing it won't be fast, sorry Bruce 8( > ... Joe -- ]] Mike Smith, Software Engineer msmith@atrad.adelaide.edu.au [[ ]] Genesis Software genesis@atrad.adelaide.edu.au [[ ]] High-speed data acquisition and (GSM mobile) 0411-222-496 [[ ]] realtime instrument control (ph/fax) +61-8-267-3039 [[ ]] "wherever you go, there you are" - Buckaroo Banzai [[
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