Date: Wed, 16 Oct 1996 12:50:51 -0600 From: Steve Passe <smp@csn.net> To: cbrown@aracnet.com Cc: smp@freebsd.org Subject: Re: dual-cpu PPRO motherboards... Message-ID: <199610161850.MAA16302@clem.systemsix.com> In-Reply-To: Your message of "Wed, 16 Oct 1996 01:13:22 PDT." <32649922.2A14@aracnet.com>
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Hi,
This terminology can get very confusing at times, can't it!
>Actually, I am talking about the APIC bus spec. It supports 255
>interrupt
>sources. The P6 (I'm not sure about the P5) atleast supports this.
>When you say IP APIC, which one are you talking about?
^^
I assume you meant IO here? The only one I have encountered is the
82093AA IO APIC. There is (was) also the 82489DX APIC which could be used
as both a "local" APIC with 80486 CPUs and as an IO APIC. But Intel doesn't
make these anymore, at least not for new systems (there may be replacement
parts available).
> I know of atleast
>3 that are commonly found on systems, probably more. Each of them
>has a different number of interrupts and capabilies. Not to mention
>systems with more than one IO APIC.
what other parts do you know of (numbers please!)
> What do you need to know? The machine I am tying this message on right
>now has
>2 IO APICs in it. Neither are PIIX/PIIX3.
The output of 'mptable', with both IO APICs enabled in the BIOS. This
will show me how the variuos INTerrupt sources are associated with
IO APIC pins, among other useful data.
You can find this program on the SMP web page at the top of the
"Various tests that you can help us run:" section:
http://www.freebsd.org/~fsmp/SMP/SMP.html
This program can be run without the SMP kernel being active, but the 2nd
IO APIC MUST be enabled in the BIOS for its assignments to show up.
Additionally, if this is an EISA machine it may or may not work, depending
on where they stuck the MP table.
Also, give me your 'dmesg' output, as well as the part #s of your IO APICs
and chipset if known.
--
Steve Passe | powered by
smp@csn.net | FreeBSD
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