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Date:      Wed, 20 Nov 1996 15:05:38 -0700
From:      Steve Passe <smp@csn.net>
To:        Peter Wemm <peter@spinner.dialix.com>
Cc:        cbrown@aracnet.com, Barney Wolff <barney@databus.com>, freebsd-smp@freebsd.org
Subject:   Re: reinventing vs copying 
Message-ID:  <199611202205.PAA27179@clem.systemsix.com>
In-Reply-To: Your message of "Thu, 21 Nov 1996 05:35:30 %2B0800." <199611202135.FAA13316@spinner.DIALix.COM> 

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Hi,

>bit registers on a per-cpu basis, ie: cpu 2 cannot see what's masked in 
>cpu 1's registers (without an APIC remote read) and so on.

beware, the P6 dropped the "Remote Read" delivery mode...

---
>- we need to be able to have the 8259's online for some (current) hardware.

I have an experimental model working where I am using ExtINT mode on APIC
INT0 to read the 8254 timer via the 8259.  Using the 8259 to pass a vector
for ONE INT source turns out to be rather painless, handling more than 1
INT via the 8259 would be ugly, you have to start managing the masks & etc.
in the 8259.  But I also realized that there is a more fundimental problem.
The 'low priority' and 'ExtInt' delivery modes are mutually exclusive!
This means that INTs deliveried via the 8259/ExtInt CANNOT be sent by
the 'low priority' delivery mode.  They either go to a specific CPU
or they can be "broadcast" (I think) to all CPUs.  This might be OK
for the 8259 timer INT, but more general INTs would be "cumbersome"
in this mode.

---
>I personally think that the right "temporary" solution for the edge 
>trigger problem is to never disable the IO apic pin (for edge only), and 
>simply wear the cost of the relatively rare occasions when the interrupts 
>*do* interrupt their own handlers.

what is this cost, panic or corruption?

--
Steve Passe	| powered by
smp@csn.net	|            FreeBSD

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