Date: Thu, 05 Dec 1996 00:32:58 +0800 From: Peter Wemm <peter@spinner.dialix.com> To: Erich Boleyn <erich@uruk.org> Cc: Terje Normann Marthinussen <Terje.N.Marthinussen@cc.uit.no>, smp@csn.net, smp@freebsd.org Subject: Re: Crashing on activating other CPUs Message-ID: <199612041632.AAA00404@spinner.DIALix.COM> In-Reply-To: Your message of "Wed, 04 Dec 1996 08:20:09 PST." <E0vVK3N-00025m-00@uruk.org>
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Erich Boleyn wrote: > > Terje Normann Marthinussen <Terje.N.Marthinussen@cc.uit.no> writes: > > > cpunumber = 0 > > instruction pointer = 0x8:0xf010d65b > > stack pointer = 0x10:0xefbfff68 > > frame pointer = 0x10:0xefbfff6c > > code segment = base 0x0, limit 0xfffff, type 0x1b > > = DPL 0, pres 1, def32 1, gran 1 > > processor eflags = interrupt enabled, IOPL = 0 > > current process = 6 (cpuidle1) > > interrupt mask = > > kernel: type 29 trap, code=0 > > ... > > The "type 29 trap" is the IPI used for SMP invalidates, I believe. We use ICU_OFFSET + 27 in the idt, so if anything it should be at vector 59. ICU_OFFSET is 32, so irq0 corresponds to idt slot #32. Entries 0-31 are partially defined by Intel and those that are not defined are reserved. Oh, wait a minute.. The IDT table is initialised with pointers to the "rsvd" handler which generates a #29 trap.. Did somebody mention not running with APIC_IO? SMP_INVLTLB is totally dependent on APIC_IO. Cheers, -Peter
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