Date: Mon, 26 May 1997 01:00:46 -0400 From: Charles Henrich <henrich@crh.cl.msu.edu> To: Brian Tao <taob@nbc.netcom.ca> Cc: freebsd-chat@FreeBSD.ORG Subject: Re: Pentium II-266Mhz Message-ID: <19970526010046.05547@crh.cl.msu.edu> In-Reply-To: <Pine.GSO.3.95.970525164111.21528x-100000@tor-adm1.nbc.netcom.ca>; from Brian Tao on Sun, May 25, 1997 at 04:42:50PM -0400 References: <19970522202155.61543@crh.cl.msu.edu> <Pine.GSO.3.95.970525164111.21528x-100000@tor-adm1.nbc.netcom.ca>
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On the subject of Re: Pentium II-266Mhz, Brian Tao stated:
> On Thu, 22 May 1997, Charles Henrich wrote:
> >
> > 8:13pm crh> dd if=/dev/zero of=/dev/null bs=1m count=1000 1000+0 records
> > in 1000+0 records out 1048576000 bytes transferred in 9.969560 secs
> > (105177762 bytes/sec)
> >
> > 8:14pm crh> dd if=/dev/zero of=/dev/null bs=128k count=8000 8000+0 records
> > in 8000+0 records out 1048576000 bytes transferred in 4.389535 secs
> > (238880886 bytes/sec)
>
> I presume the first involves the CPU going to main memory, while the
> second fits entirely in L2 cache? What's the bandwidth over a PCI bus?
> 132MB/sec? It looks like the CPU can push almost twice that. Time for
> a 100-MHz bus or a separate CPU-to-RAM bus...
Yep, thats been my gripe for a long time. The PCI bus sucks, it needs to be
twice the bandwidth of the CPU (or more!) for growth, and memory access times
need to go down. I would bet if someone did a formal study, that a huge
percentage of Intel cycles are spent waiting for loads.. Speed up the
Pentium(Pro/PII) without changing a thing, except the motherboad!
-Crh
Charles Henrich Michigan State University henrich@msu.edu
http://pilot.msu.edu/~henrich
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