Date: Sat, 19 Jun 1999 12:40:27 -0700 From: Aaron Smith <aaron-fbsd@mutex.org> To: Achim Patzner <ap@bnc.net> Cc: freebsd-smp@FreeBSD.ORG Subject: Re: P2B-DS and its statclock/APM/whatever Message-ID: <199906191940.MAA94507@sigma.veritas.com> In-Reply-To: Your message of "Sat, 19 Jun 1999 20:57:43 %2B0200." <19990619205743.A511@bnc.net>
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On Sat, 19 Jun 1999 20:57:43 +0200, Achim Patzner writes:
>Ok, you got me. As I had a scheduled downtime today, I upgraded the BIOS of
>my beloved gemini.bnc.net from 1006 to 1009. Guess what: No matter how I'm
>configuring APM BIOS settings or the apm0 device, my top is looking like
>this now:
>
> PID USERNAME PRI NICE SIZE RES STATE C TIME WCPU CPU COMMAND
> 338 root 10 0 4628K 1448K nanslp 0 0:01 0.00% 0.00% wcol
don't downgrade, just try this patch from Tor Egge. it worked great for my
P2B-DS (bios rev 1008).
Aaron
----Next_Part(Tue_Jun_15_20:53:50_1999)--
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Index: sys/pci/pcisupport.c
===================================================================
RCS file: /home/ncvs/src/sys/pci/pcisupport.c,v
retrieving revision 1.86.2.8
diff -u -r1.86.2.8 pcisupport.c
--- pcisupport.c 1999/05/26 16:39:42 1.86.2.8
+++ pcisupport.c 1999/06/06 20:31:02
@@ -213,7 +213,87 @@
tag->secondarybus = tag->subordinatebus = secondarybus + 1;
}
+#ifdef SMP
static void
+fix_82371ab_power_management(pcici_t tag)
+{
+ int pmba;
+ int devctl;
+ int devctl_changed;
+ int devrese;
+ int devresg;
+
+#define PMBA_CONFIG_OFFSET 0x40
+#define PMBA_TO_IO(addr) (addr & 0xffc0)
+#define DEVRESE_OFFSET 0x68
+#define DEVRESG_OFFSET 0x70
+#define DEVRES_MONITOR_ENABLE (1 << 20)
+#define DEVCTL_IO_OFFSET 0x2c
+#define DEVCTL_TRAP_DEV12 (1 << 24)
+#define DEVCTL_TRAP_DEV13 (1 << 25)
+#define RTC_IOADDR 0x70
+
+ pmba = pci_cfgread(tag, PMBA_CONFIG_OFFSET, 4);
+
+ devctl = inl(PMBA_TO_IO(pmba) + DEVCTL_IO_OFFSET);
+ devctl_changed = 0;
+
+ devrese = pci_cfgread(tag, DEVRESE_OFFSET, 2) |
+ (pci_cfgread(tag, DEVRESE_OFFSET + 2, 1) << 16);
+
+ if ((devrese & DEVRES_MONITOR_ENABLE) != 0 &&
+ ((devrese >> 16) & 15) <= 7 &&
+ (devrese & 0xffff) == RTC_IOADDR &&
+ (devctl & DEVCTL_TRAP_DEV12) != 0) {
+
+ devrese &= ~DEVRES_MONITOR_ENABLE;
+ devctl &= ~DEVCTL_TRAP_DEV12;
+ devctl_changed = 1;
+
+ pci_cfgwrite(tag, DEVRESE_OFFSET, 2, (devrese & 0xffff));
+ pci_cfgwrite(tag, DEVRESE_OFFSET + 2, 1,
+ (devrese >> 16) & 0xff);
+
+ printf("Disabled Device 12 trap SMI for access to RTC chip\n");
+ }
+
+ devresg = pci_cfgread(tag, DEVRESG_OFFSET, 2) |
+ (pci_cfgread(tag, DEVRESG_OFFSET + 2, 1) << 16);
+
+ if ((devresg & DEVRES_MONITOR_ENABLE) != 0 &&
+ ((devresg >> 16) & 15) <= 7 &&
+ (devresg & 0xffff) == RTC_IOADDR &&
+ (devctl & DEVCTL_TRAP_DEV13) != 0) {
+
+ devresg &= ~DEVRES_MONITOR_ENABLE;
+ devctl &= ~DEVCTL_TRAP_DEV13;
+ devctl_changed = 1;
+
+ pci_cfgwrite(tag, DEVRESG_OFFSET, 2, (devresg & 0xffff));
+ pci_cfgwrite(tag, DEVRESG_OFFSET + 2, 1,
+ (devresg >> 16) & 0xff);
+
+ printf("Disabled Device 13 trap SMI for access to RTC chip\n");
+ }
+
+ if (devctl_changed != 0) {
+ outl(PMBA_TO_IO(pmba) + DEVCTL_IO_OFFSET, devctl);
+ }
+
+#undef PMBA_CONFIG_OFFSET
+#undef PMBA_TO_IO
+#undef DEVRESE_OFFSET
+#undef DEVRESG_OFFSET
+#undef DEVRES_MONITOR_ENABLE
+#undef DEVCTL_IO_OFFSET
+#undef DEVCTL_TRAP_DEV12
+#undef DEVCTL_TRAP_DEV13
+#undef RTC_IOADDR
+}
+#endif
+
+
+static void
fixwsc_natoma(pcici_t tag)
{
int pmccfg;
@@ -284,6 +364,9 @@
case 0x71108086:
return ("Intel 82371AB PCI to ISA bridge");
case 0x71138086:
+#if defined(SMP)
+ fix_82371ab_power_management(tag);
+#endif
return ("Intel 82371AB Power management controller");
case 0x71808086:
return ("Intel 82443LX host to PCI bridge");
----Next_Part(Tue_Jun_15_20:53:50_1999)----
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