Date: Tue, 29 Jun 1999 13:08:28 -0600 (MDT) From: Kevin Van Maren <vanmaren@fast.cs.utah.edu> To: freebsd-smp@FreeBSD.ORG, tich@ma.ikos.com, vanmaren@cs.utah.edu Subject: Re: high-efficiency SMP locks - submission for review Message-ID: <199906291908.NAA08028@fast.cs.utah.edu>
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> No, you can have a non-aligned locked access - there's a bunch of
> complex and ugly stuff ("split locks", the SPLCK# bus signal) in
> the P6 bus protocol to support this. But don't do it if you can
> possibly avoid it - it's inefficient, and since it exercises arcane
> features of the hardware, it could be buggy.
My understanding is that it is only guaranteed to be atomic for the
processor family if it is naturally-aligned, although current
processors ALSO provide atomic operatings for unaligned accesses.
My point is that we should not rely on unaligned accesses being
atomic, as per intel documentation.
> Also the claim that x86 takes interrupts only at instruction boundaries is
> only half-true - I believe you can take an interrupt in the middle of a
> string instruction, it will leave the registers in a suitable state so that
> restarting the string instruction will resume where it left off.
Yes, because the string instructions are not a single instrucition.
It looks like one, but it is really a micro-coded loop. This can be
interrupted after each loop iteration (decrement/increment and
store/copy are done atomically).
This wasn't always the case: I believe on the 8088, it was non-
interruptable, however, they had to fix it to deal with crossing
page boundaries on the i386.
Kevin
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