Date: Mon, 4 Feb 2002 13:55:12 +0200 (EET) From: Narvi <narvi@haldjas.folklore.ee> To: Peter Wemm <peter@wemm.org> Cc: "'freebsd-current@freebsd.org'" <freebsd-current@FreeBSD.ORG> Subject: Re: AMD AGP Bug Message-ID: <20020204132551.B7603-100000@haldjas.folklore.ee> In-Reply-To: <20020201083417.C3FFC3809@overcee.wemm.org>
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On Fri, 1 Feb 2002, Peter Wemm wrote: > - AMD write cache allocation due to speculative writes being cancelled and > then written back later vs no cache snooping on AGP regions. I'm somewhat > perplexed about this issue, there's lots of conflicting info going around, > a good deal of it which does not make much sense [to me :-)]. I really > dont see what PSE has to do with this for several reasons.. if the page/ > region is cacheable, why does a 4MB vs 4K page make any difference? > cacheable vs no-cache-snooping is a recipe for disaster.. why would 4K > pages on a non-coherent region be safer? Or is the problem that write > allocation happens on uncacheable/non-write-back regions in 4MB pages? Or > something else? > Speculative writes can only happen to pages in the TLB (so you don't get speculative TLB misses and replacements), not having a large amount of 4M pages around in the TLB means that addresses covered by these can't possibly be involved in speculative writes. I personaly suspect the reason the cache line flushes of speculatively "written to" cache lines derive from the AMD-s use of MOESI coherency and mapping that to actual bits. Another "minor" side effect is that you get direct cache-to-cahce transfers in SMP systems for shared data. Sander > Cheers, > -Peter > -- > Peter Wemm - peter@FreeBSD.org; peter@yahoo-inc.com; peter@netplex.com.au > "All of this is for nothing if we don't go to the stars" - JMS/B5 > To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-current" in the body of the message
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