Date: Fri, 1 Mar 2002 22:18:16 -0800 From: Brooks Davis <brooks@one-eyed-alien.net> To: mobile@freebsd.org Subject: big wi MFC patch Message-ID: <20020301221816.A29315@Odin.AC.HMC.Edu>
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Please review and test the following patch. It fully MFC's all applicable
changes from current. Once this patch is applied, the only differences
between the version in current and the version in stable are due to
changes in APIs (locking, interface naming, NEWCARD, etc). This patch
assume you have the very latest sources (it depends on a style commit
I made a few hours ago.)
The significant changes in this patch are:
- Prism II detection from NetBSD.
- Prism 2.5 support.
- 128-bit crypto fixes for Prism chipsets.
I plan to commit this Monday the 4th if there are no objections.
-- Brooks
Index: if_wi.c
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /home/ncvs/src/sys/i386/isa/Attic/if_wi.c,v
retrieving revision 1.18.2.15
diff -u -r1.18.2.15 if_wi.c
--- if_wi.c 2 Mar 2002 01:41:42 -0000 1.18.2.15
+++ if_wi.c 2 Mar 2002 02:45:53 -0000
@@ -123,6 +123,13 @@
static u_int8_t wi_mcast_addr[6] =3D { 0x01, 0x60, 0x1D, 0x00, 0x01, 0x00 =
};
#endif
=20
+/*
+ * The following is for compatibility with NetBSD, but should really be
+ * brought in from NetBSD en toto.
+ */
+#define le16toh(a) (a)
+#define LE16TOH(a)
+
static void wi_intr __P((void *));
static void wi_reset __P((struct wi_softc *));
static int wi_ioctl __P((struct ifnet *, u_long, caddr_t));
@@ -168,6 +175,7 @@
static void wi_free __P((device_t));
=20
static int wi_get_cur_ssid __P((struct wi_softc *, char *, int *));
+static void wi_get_id __P((struct wi_softc *, device_t));
static int wi_media_change __P((struct ifnet *));
static void wi_media_status __P((struct ifnet *, struct ifmediareq *));
=20
@@ -208,13 +216,15 @@
=20
static struct {
unsigned int vendor,device;
+ int bus_type;
char *desc;
} pci_ids[] =3D {
- {0x1638, 0x1100, "PRISM2STA PCI WaveLAN/IEEE 802.11"},
- {0x1385, 0x4100, "Netgear MA301 PCI IEEE 802.11b"},
- {0x16ab, 0x1101, "GLPRISM2 PCI WaveLAN/IEEE 802.11"},
- {0x16ab, 0x1102, "Linksys WDT11 PCI IEEE 802.11b"},
- {0, 0, NULL}
+ {0x1638, 0x1100, WI_BUS_PCI_PLX, "PRISM2STA PCI WaveLAN/IEEE 802.11"},
+ {0x1385, 0x4100, WI_BUS_PCI_PLX, "Netgear MA301 PCI IEEE 802.11b"},
+ {0x16ab, 0x1101, WI_BUS_PCI_PLX, "GLPRISM2 PCI WaveLAN/IEEE 802.11"},
+ {0x16ab, 0x1102, WI_BUS_PCI_PLX, "Linksys WDT11 PCI IEEE 802.11b"},
+ {0x1260, 0x3873, WI_BUS_PCI_NATIVE, "Linksys WMP11 PCI Prism2.5"},
+ {0, 0, 0, NULL}
};
#endif
=20
@@ -236,6 +246,7 @@
=20
sc =3D device_get_softc(dev);
sc->wi_gone =3D 0;
+ sc->wi_bus_type =3D WI_BUS_PCCARD;
=20
error =3D wi_alloc(dev, 0);
if (error)
@@ -264,6 +275,7 @@
if ((pci_get_vendor(dev) =3D=3D pci_ids[i].vendor) &&
(pci_get_device(dev) =3D=3D pci_ids[i].device)) {
sc->wi_prism2 =3D 1;
+ sc->wi_bus_type =3D pci_ids[i].bus_type;
device_set_desc(dev, pci_ids[i].desc);
return (0);
}
@@ -310,33 +322,9 @@
{
struct wi_softc *sc;
int error;
- u_int32_t flags;
=20
sc =3D device_get_softc(dev);
=20
- /*
- * XXX: quick hack to support Prism II chip.
- * Currently, we need to set a flags in pccard.conf to specify
- * which type chip is used.
- *
- * We need to replace this code in a future.
- * It is better to use CIS than using a flag.
- */
- flags =3D device_get_flags(dev);
-#define WI_FLAGS_PRISM2 0x10000
- if (flags & WI_FLAGS_PRISM2) {
- sc->wi_prism2 =3D 1;
- if (bootverbose) {
- device_printf(dev, "found PrismII chip\n");
- }
- }
- else {
- sc->wi_prism2 =3D 0;
- if (bootverbose) {
- device_printf(dev, "found Lucent chip\n");
- }
- }
-
error =3D wi_alloc(dev, 0);
if (error) {
device_printf(dev, "wi_alloc() failed! (%d)\n", error);
@@ -353,6 +341,7 @@
u_int32_t command, wanted;
u_int16_t reg;
int error;
+ int timeout;
=20
sc =3D device_get_softc(dev);
=20
@@ -366,53 +355,76 @@
return (ENXIO);
}
=20
- error =3D wi_alloc(dev, WI_PCI_IORES);
- if (error)
- return (error);
+ if (sc->wi_bus_type !=3D WI_BUS_PCI_NATIVE) {
+ error =3D wi_alloc(dev, WI_PCI_IORES);
+ if (error)
+ return (error);
=20
- /* Make sure interrupts are disabled. */
- CSR_WRITE_2(sc, WI_INT_EN, 0);
- CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
+ /* Make sure interrupts are disabled. */
+ CSR_WRITE_2(sc, WI_INT_EN, 0);
+ CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
=20
- /* We have to do a magic PLX poke to enable interrupts */
- sc->local_rid =3D WI_PCI_LOCALRES;
- sc->local =3D bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->local_rid,
- 0, ~0, 1, RF_ACTIVE);
- sc->wi_localtag =3D rman_get_bustag(sc->local);
- sc->wi_localhandle =3D rman_get_bushandle(sc->local);
- command =3D bus_space_read_4(sc->wi_localtag, sc->wi_localhandle,
- WI_LOCAL_INTCSR);
- command |=3D WI_LOCAL_INTEN;
- bus_space_write_4(sc->wi_localtag, sc->wi_localhandle,
- WI_LOCAL_INTCSR, command);
- bus_release_resource(dev, SYS_RES_IOPORT, sc->local_rid, sc->local);
- sc->local =3D NULL;
-=09
- sc->mem_rid =3D WI_PCI_MEMRES;
- sc->mem =3D bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->mem_rid,
- 0, ~0, 1, RF_ACTIVE);
- if (sc->mem =3D=3D NULL) {
- device_printf(dev, "couldn't allocate memory\n");
- wi_free(dev);
- return (ENXIO);
- }
- sc->wi_bmemtag =3D rman_get_bustag(sc->mem);
- sc->wi_bmemhandle =3D rman_get_bushandle(sc->mem);
+ /* We have to do a magic PLX poke to enable interrupts */
+ sc->local_rid =3D WI_PCI_LOCALRES;
+ sc->local =3D bus_alloc_resource(dev, SYS_RES_IOPORT,
+ &sc->local_rid, 0, ~0, 1, RF_ACTIVE);
+ sc->wi_localtag =3D rman_get_bustag(sc->local);
+ sc->wi_localhandle =3D rman_get_bushandle(sc->local);
+ command =3D bus_space_read_4(sc->wi_localtag, sc->wi_localhandle,
+ WI_LOCAL_INTCSR);
+ command |=3D WI_LOCAL_INTEN;
+ bus_space_write_4(sc->wi_localtag, sc->wi_localhandle,
+ WI_LOCAL_INTCSR, command);
+ bus_release_resource(dev, SYS_RES_IOPORT, sc->local_rid,
+ sc->local);
+ sc->local =3D NULL;
=20
- /*
- * From Linux driver:
- * Write COR to enable PC card
- * This is a subset of the protocol that the pccard bus code
- * would do.
- */
- CSM_WRITE_1(sc, WI_COR_OFFSET, WI_COR_VALUE);=20
- reg =3D CSM_READ_1(sc, WI_COR_OFFSET);
- if (reg !=3D WI_COR_VALUE) {
- device_printf(dev,
- "CSM_READ_1(WI_COR_OFFSET) "
- "wanted %d, got %d\n", WI_COR_VALUE, reg);
- wi_free(dev);
- return (ENXIO);
+ sc->mem_rid =3D WI_PCI_MEMRES;
+ sc->mem =3D bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->mem_rid,
+ 0, ~0, 1, RF_ACTIVE);
+ if (sc->mem =3D=3D NULL) {
+ device_printf(dev, "couldn't allocate memory\n");
+ wi_free(dev);
+ return (ENXIO);
+ }
+ sc->wi_bmemtag =3D rman_get_bustag(sc->mem);
+ sc->wi_bmemhandle =3D rman_get_bushandle(sc->mem);
+
+ /*
+ * From Linux driver:
+ * Write COR to enable PC card
+ * This is a subset of the protocol that the pccard bus code
+ * would do.
+ */
+ CSM_WRITE_1(sc, WI_COR_OFFSET, WI_COR_VALUE);
+ reg =3D CSM_READ_1(sc, WI_COR_OFFSET);
+ if (reg !=3D WI_COR_VALUE) {
+ device_printf(dev, "CSM_READ_1(WI_COR_OFFSET) "
+ "wanted %d, got %d\n", WI_COR_VALUE, reg);
+ wi_free(dev);
+ return (ENXIO);
+ }
+ } else {
+ error =3D wi_alloc(dev, WI_PCI_LMEMRES);
+ if (error)
+ return (error);
+
+ CSR_WRITE_2(sc, WI_HFA384X_PCICOR_OFF, 0x0080);
+ DELAY(250000);
+
+ CSR_WRITE_2(sc, WI_HFA384X_PCICOR_OFF, 0x0000);
+ DELAY(500000);
+
+ timeout=3D2000000;
+ while ((--timeout > 0) &&
+ (CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY))
+ DELAY(10);
+
+ if (timeout =3D=3D 0) {
+ device_printf(dev, "couldn't reset prism2.5 core.\n");
+ wi_free(dev);
+ return(ENXIO);
+ }
}
=20
CSR_WRITE_2(sc, WI_HFA384X_SWSUPPORT0_OFF, WI_PRISM2STA_MAGIC);
@@ -474,8 +486,9 @@
bcopy((char *)&mac.wi_mac_addr,
(char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
=20
- device_printf(dev, "Ethernet address: %6D\n",
- sc->arpcom.ac_enaddr, ":");
+ device_printf(dev, "802.11 address: %6D\n", sc->arpcom.ac_enaddr, ":");
+
+ wi_get_id(sc, dev);
=20
ifp->if_softc =3D sc;
ifp->if_unit =3D sc->wi_unit;
@@ -533,8 +546,8 @@
=20
if (bootverbose) {
device_printf(sc->dev,
- __FUNCTION__ ":wi_has_wep =3D %d\n",
- sc->wi_has_wep);
+ "%s:wi_has_wep =3D %d\n",
+ __func__, sc->wi_has_wep);
}
=20
bzero((char *)&sc->wi_stats, sizeof(sc->wi_stats));
@@ -575,6 +588,80 @@
}
=20
static void
+wi_get_id(sc, dev)
+ struct wi_softc *sc;
+ device_t dev;
+{
+ struct wi_ltv_ver ver;
+
+ /* getting chip identity */
+ memset(&ver, 0, sizeof(ver));
+ ver.wi_type =3D WI_RID_CARDID;
+ ver.wi_len =3D 5;
+ wi_read_record(sc, (struct wi_ltv_gen *)&ver);
+ device_printf(dev, "using ");
+ switch (le16toh(ver.wi_ver[0])) {
+ case WI_NIC_EVB2:
+ printf("RF:PRISM2 MAC:HFA3841");
+ sc->wi_prism2 =3D 1;
+ break;
+ case WI_NIC_HWB3763:
+ printf("RF:PRISM2 MAC:HFA3841 CARD:HWB3763 rev.B");
+ sc->wi_prism2 =3D 1;
+ break;
+ case WI_NIC_HWB3163:
+ printf("RF:PRISM2 MAC:HFA3841 CARD:HWB3163 rev.A");
+ sc->wi_prism2 =3D 1;
+ break;
+ case WI_NIC_HWB3163B:
+ printf("RF:PRISM2 MAC:HFA3841 CARD:HWB3163 rev.B");
+ sc->wi_prism2 =3D 1;
+ break;
+ case WI_NIC_EVB3:
+ printf("RF:PRISM2 MAC:HFA3842");
+ sc->wi_prism2 =3D 1;
+ break;
+ case WI_NIC_HWB1153:
+ printf("RF:PRISM1 MAC:HFA3841 CARD:HWB1153");
+ sc->wi_prism2 =3D 1;
+ break;
+ case WI_NIC_P2_SST:
+ printf("RF:PRISM2 MAC:HFA3841 CARD:HWB3163-SST-flash");
+ sc->wi_prism2 =3D 1;
+ break;
+ case WI_NIC_PRISM2_5:
+ printf("RF:PRISM2.5 MAC:ISL3873");
+ sc->wi_prism2 =3D 1;
+ break;
+ case WI_NIC_3874A:
+ printf("RF:PRISM2.5 MAC:ISL3874A(PCI)");
+ sc->wi_prism2 =3D 1;
+ break;
+ default:
+ printf("Lucent chip or unknown chip\n");
+ sc->wi_prism2 =3D 0;
+ break;
+ }
+
+ if (sc->wi_prism2) {
+ /* try to get prism2 firm version */
+ memset(&ver, 0, sizeof(ver));
+ ver.wi_type =3D WI_RID_IDENT;
+ ver.wi_len =3D 5;
+ wi_read_record(sc, (struct wi_ltv_gen *)&ver);
+ LE16TOH(ver.wi_ver[1]);
+ LE16TOH(ver.wi_ver[2]);
+ LE16TOH(ver.wi_ver[3]);
+ printf(", Firmware: %d.%d variant %d\n", ver.wi_ver[2],
+ ver.wi_ver[3], ver.wi_ver[1]);
+ sc->wi_prism2_ver =3D ver.wi_ver[2] * 100 +
+ ver.wi_ver[3] * 10 + ver.wi_ver[1];
+ }
+
+ return;
+}
+
+static void
wi_rxeof(sc)
struct wi_softc *sc;
{
@@ -848,6 +935,7 @@
DELAY(10*1000); /* 10 m sec */
}
if (i =3D=3D 0) {
+ device_printf(sc->dev, "wi_cmd: busy bit won't clear.\n" );
return(ETIMEDOUT);
}
=20
@@ -861,8 +949,8 @@
* Wait for 'command complete' bit to be
* set in the event status register.
*/
- s =3D CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_CMD;
- if (s) {
+ s =3D CSR_READ_2(sc, WI_EVENT_STAT);
+ if (s & WI_EV_CMD) {
/* Ack the event and read result code. */
s =3D CSR_READ_2(sc, WI_STATUS);
CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD);
@@ -874,9 +962,12 @@
return(EIO);
break;
}
+ DELAY(WI_DELAY);
}
=20
if (i =3D=3D WI_TIMEOUT) {
+ device_printf(sc->dev,
+ "timeout in wi_cmd %x; event status %x\n", cmd, s);
return(ETIMEDOUT);
}
=20
@@ -893,7 +984,7 @@
for (i =3D 0; i < WI_INIT_TRIES; i++) {
if (wi_cmd(sc, WI_CMD_INI, 0) =3D=3D 0)
break;
- DELAY(50 * 1000); /* 50ms */
+ DELAY(WI_DELAY * 1000);
}
if (i =3D=3D WI_INIT_TRIES)
device_printf(sc->dev, "init failed\n");
@@ -1042,16 +1133,19 @@
case WI_RID_DEFLT_CRYPT_KEYS:
{
int error;
+ int keylen;
struct wi_ltv_str ws;
struct wi_ltv_keys *wk =3D
(struct wi_ltv_keys *)ltv;
=20
+ keylen =3D wk->wi_keys[sc->wi_tx_key].wi_keylen;
+
for (i =3D 0; i < 4; i++) {
- ws.wi_len =3D 4;
+ bzero(&ws, sizeof(ws));
+ ws.wi_len =3D (keylen > 5) ? 8 : 4;
ws.wi_type =3D WI_RID_P2_CRYPT_KEY0 + i;
memcpy(ws.wi_str,
- &wk->wi_keys[i].wi_keydat, 5);
- ws.wi_str[5] =3D '\0';
+ &wk->wi_keys[i].wi_keydat, keylen);
error =3D wi_write_record(sc,
(struct wi_ltv_gen *)&ws);
if (error)
@@ -1108,6 +1202,7 @@
status =3D CSR_READ_2(sc, offreg);
if (!(status & (WI_OFF_BUSY|WI_OFF_ERR)))
break;
+ DELAY(WI_DELAY);
}
=20
if (i =3D=3D WI_TIMEOUT) {
@@ -1214,6 +1309,7 @@
for (i =3D 0; i < WI_TIMEOUT; i++) {
if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_ALLOC)
break;
+ DELAY(WI_DELAY);
}
=20
if (i =3D=3D WI_TIMEOUT) {
@@ -1962,23 +2058,45 @@
}
=20
static int
-wi_alloc(dev, io_rid)
+wi_alloc(dev, rid)
device_t dev;
- int io_rid;
+ int rid;
{
struct wi_softc *sc =3D device_get_softc(dev);
=20
- sc->iobase_rid =3D io_rid;
- sc->iobase =3D bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->iobase_rid,
- 0, ~0, 1, RF_ACTIVE);
- if (!sc->iobase) {
- device_printf(dev, "No I/O space?!\n");
- return (ENXIO);
+ if (sc->wi_bus_type !=3D WI_BUS_PCI_NATIVE) {
+ sc->iobase_rid =3D rid;
+ sc->iobase =3D bus_alloc_resource(dev, SYS_RES_IOPORT,
+ &sc->iobase_rid, 0, ~0, (1 << 6),
+ rman_make_alignment_flags(1 << 6) | RF_ACTIVE);
+ if (!sc->iobase) {
+ device_printf(dev, "No I/O space?!\n");
+ return (ENXIO);
+ }
+
+ sc->wi_io_addr =3D rman_get_start(sc->iobase);
+ sc->wi_btag =3D rman_get_bustag(sc->iobase);
+ sc->wi_bhandle =3D rman_get_bushandle(sc->iobase);
+ } else {
+ sc->mem_rid =3D rid;
+ sc->mem =3D bus_alloc_resource(dev, SYS_RES_MEMORY,
+ &sc->mem_rid, 0, ~0, 1, RF_ACTIVE);
+
+ if (!sc->mem) {
+ device_printf(dev, "No Mem space on prism2.5?\n");
+ return (ENXIO);
+ }
+
+ sc->wi_btag =3D rman_get_bustag(sc->mem);
+ sc->wi_bhandle =3D rman_get_bushandle(sc->mem);
}
=20
+
sc->irq_rid =3D 0;
sc->irq =3D bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid,
- 0, ~0, 1, RF_ACTIVE);
+ 0, ~0, 1, RF_ACTIVE |
+ ((sc->wi_bus_type =3D=3D WI_BUS_PCCARD) ? 0 : RF_SHAREABLE));
+
if (!sc->irq) {
wi_free(dev);
device_printf(dev, "No irq?!\n");
@@ -1987,9 +2105,6 @@
=20
sc->dev =3D dev;
sc->wi_unit =3D device_get_unit(dev);
- sc->wi_io_addr =3D rman_get_start(sc->iobase);
- sc->wi_btag =3D rman_get_bustag(sc->iobase);
- sc->wi_bhandle =3D rman_get_bushandle(sc->iobase);
=20
return (0);
}
Index: if_wireg.h
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
RCS file: /home/ncvs/src/sys/i386/isa/Attic/if_wireg.h,v
retrieving revision 1.8.2.2
diff -u -r1.8.2.2 if_wireg.h
--- if_wireg.h 25 Aug 2001 00:48:25 -0000 1.8.2.2
+++ if_wireg.h 2 Mar 2002 00:36:03 -0000
@@ -135,10 +135,13 @@
int wi_nextitem;
#endif
struct callout_handle wi_stat_ch;
- int wi_prism2; /* set to 1 if it uses a Prism II chip */
+ int wi_prism2;
+ int wi_prism2_ver;
+ int wi_bus_type; /* Bus attachment type */
};
=20
-#define WI_TIMEOUT 65536
+#define WI_DELAY 5
+#define WI_TIMEOUT (500000/WI_DELAY) /* 500 ms */
=20
#define WI_PORT0 0
#define WI_PORT1 1
@@ -147,6 +150,7 @@
#define WI_PORT4 4
#define WI_PORT5 5
=20
+#define WI_PCI_LMEMRES 0x10 /* PCI Memory (native PCI implementations) */
#define WI_PCI_LOCALRES 0x14 /* The PLX chip's local registers */
#define WI_PCI_MEMRES 0x18 /* The PCCard's attribute memory */
#define WI_PCI_IORES 0x1C /* The PCCard's I/O space */
@@ -155,6 +159,7 @@
#define WI_LOCAL_INTEN 0x40 /* poke this into INTCSR */
#define WI_HFA384X_SWSUPPORT0_OFF 0x28
#define WI_PRISM2STA_MAGIC 0x4A2D
+#define WI_HFA384X_PCICOR_OFF 0x26
=20
/* Default port: 0 (only 0 exists on stations) */
#define WI_DEFAULT_PORT (WI_PORT0 << 8)
@@ -183,29 +188,38 @@
=20
#define WI_DEFAULT_CHAN 3
=20
+#define WI_BUS_PCCARD 0 /* pccard device */
+#define WI_BUS_PCI_PLX 1 /* PCI card w/ PLX PCI/PCMICA bridge */
+#define WI_BUS_PCI_NATIVE 2 /* native PCI device (Prism 2.5) */
+
/*
* register space access macros
*/
-#define CSR_WRITE_4(sc, reg, val) \
- bus_space_write_4(sc->wi_btag, sc->wi_bhandle, reg, val)
-#define CSR_WRITE_2(sc, reg, val) \
- bus_space_write_2(sc->wi_btag, sc->wi_bhandle, reg, val)
-#define CSR_WRITE_1(sc, reg, val) \
- bus_space_write_1(sc->wi_btag, sc->wi_bhandle, reg, val)
-
-#define CSR_READ_4(sc, reg) \
- bus_space_read_4(sc->wi_btag, sc->wi_bhandle, reg)
-#define CSR_READ_2(sc, reg) \
- bus_space_read_2(sc->wi_btag, sc->wi_bhandle, reg)
-#define CSR_READ_1(sc, reg) \
- bus_space_read_1(sc->wi_btag, sc->wi_bhandle, reg)
+#define CSR_WRITE_4(sc, reg, val) \
+ bus_space_write_4((sc)->wi_btag, (sc)->wi_bhandle, \
+ (sc)->wi_bus_type =3D=3D WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)
+#define CSR_WRITE_2(sc, reg, val) \
+ bus_space_write_2((sc)->wi_btag, (sc)->wi_bhandle, \
+ (sc)->wi_bus_type =3D=3D WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)
+#define CSR_WRITE_1(sc, reg, val) \
+ bus_space_write_1((sc)->wi_btag, (sc)->wi_bhandle, \
+ (sc)->wi_bus_type =3D=3D WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)
+
+#define CSR_READ_4(sc, reg) \
+ bus_space_read_4((sc)->wi_btag, (sc)->wi_bhandle, \
+ (sc)->wi_bus_type =3D=3D WI_BUS_PCI_NATIVE ? (reg)*2 : (reg))
+#define CSR_READ_2(sc, reg) \
+ bus_space_read_2((sc)->wi_btag, (sc)->wi_bhandle, \
+ (sc)->wi_bus_type =3D=3D WI_BUS_PCI_NATIVE ? (reg)*2 : (reg))
+#define CSR_READ_1(sc, reg) \
+ bus_space_read_1((sc)->wi_btag, (sc)->wi_bhandle, \
+ (sc)->wi_bus_type =3D=3D WI_BUS_PCI_NATIVE ? (reg)*2 : (reg))
=20
#define CSM_WRITE_1(sc, off, val) \
- bus_space_write_1(sc->wi_bmemtag, sc->wi_bmemhandle, off, val)
+ bus_space_write_1((sc)->wi_bmemtag, (sc)->wi_bmemhandle, off, val)
=20
#define CSM_READ_1(sc, off) \
- bus_space_read_1(sc->wi_bmemtag, sc->wi_bmemhandle, off)
-
+ bus_space_read_1((sc)->wi_bmemtag, (sc)->wi_bmemhandle, off)
=20
/*
* The WaveLAN/IEEE cards contain an 802.11 MAC controller which Lucent
@@ -438,6 +452,26 @@
u_int16_t wi_type;
u_int16_t wi_mem_ram;
u_int16_t wi_mem_nvram;
+};
+
+/*
+ * NIC Identification (0xFD0B)
+ */
+#define WI_RID_CARDID 0xFD0B
+#define WI_RID_IDENT 0xFD20
+struct wi_ltv_ver {
+ u_int16_t wi_len;
+ u_int16_t wi_type;
+ u_int16_t wi_ver[4];
+#define WI_NIC_EVB2 0x8000
+#define WI_NIC_HWB3763 0x8001
+#define WI_NIC_HWB3163 0x8002
+#define WI_NIC_HWB3163B 0x8003
+#define WI_NIC_EVB3 0x8004
+#define WI_NIC_HWB1153 0x8007
+#define WI_NIC_P2_SST 0x8008 /* Prism2 with SST flush */
+#define WI_NIC_PRISM2_5 0x800C
+#define WI_NIC_3874A 0x8013 /* Prism2.5 Mini-PCI */
};
=20
/*
--=20
Any statement of the form "X is the one, true Y" is FALSE.
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