Date: Mon, 19 May 2003 00:45:09 +1000 (EST) From: Bruce Evans <bde@zeta.org.au> To: jimd@siu.edu Cc: freebsd-current@freebsd.org Subject: Re: Current-5.1-BETA hangs with SMP/HTT/APIC Message-ID: <20030519000704.K19959@gamplex.bde.org> In-Reply-To: <20030518034907.S28148@freebsd2.localnet10> References: <20030518034907.S28148@freebsd2.localnet10>
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On Sun, 18 May 2003 jimd_NOSPAM@siu.edu wrote:
> I have an MSI 655-MAX (SiS 655/963) motherboard (which is HTT capable).
> When I boot a re-compiled kernel with SMP and APIC enabled, the process
> hangs at/after "APIC_IO: Testing 8254 interrupt delivery". (I had to
> disable acpi.o in order to be able to use my Soundblaster Live! card)
Hangs here probably mean that RTC interrupts don't work. The message lies
slightly -- the test is actually of both RTC and i8254 interrupt delivery,
with i8254 interrupt delivery not tested at all until 5 or 6 RTC interrupts
have been delivered.
I don't know why RTC interrupts wouldn't be delivered, but in my kernel
all interrupts are hard to deliver here, so I only arranged for delivery
of i8254 interrupts and simplified the test to not need RTC interrupts.
This simplification should work in all kernels.
%%%
Index: clock.c
===================================================================
RCS file: /home/ncvs/src/sys/i386/isa/clock.c,v
retrieving revision 1.191
diff -u -2 -r1.191 clock.c
--- clock.c 4 Dec 2002 13:46:49 -0000 1.191
+++ clock.c 26 Apr 2003 12:07:37 -0000
@@ -1076,8 +1799,6 @@
#ifdef APIC_IO
if (apic_8254_trial) {
-
printf("APIC_IO: Testing 8254 interrupt delivery\n");
- while (read_intr_count(8) < 6)
- ; /* nothing */
+ DELAY(100000);
if (read_intr_count(apic_8254_intr) < 3) {
/*
%%%
Some details: the old code waits for hopefully at least 5 or 6 RTC
interrupts. It is sloppy and may lose if several RTC interrupts have
already occurred, but this probably doesn't happen in practice. The
RTC interrupt frequency is approx. 128 Hz, so waiting for 5-6 RTC
interrupts is almost equivalent to waiting for 39-47 msec. My version
waits for 100 msec instead. The i8254 counter should be reliable at
this point although i8254 interrupts might not be. The i8254 interrupt
frequency is approximately HZ Hz. For the default configuration of
HZ = 100, there should be 3-5 i8254 interrupts during the wait time
of 39-47 msec. The magic number of 3 in the test is the same as the
3 in "3-5". The above code seems to be quite broken for values of HZ
not much smaller than the default, but configuring such values is
unusual.
To avoid the magic numbers, rewrite the test to check that there is
at least 1 i8254 interrupt after the first detected reversal of the
i8254 countdown.
Bruce
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